RE: gEDA-user: putting it all together

["Jason Doege" <jdoege@inovys.com>]

In particular, LUTs will have to be re-mapped to boolean functions.

The person who first requested this got a little irritated when pressed
about optimization, but I think there will need to be at least a minimum
cost analysis done for proper cell selection. Then there is the issue of
legal cell selection which is to say cell size selection. Some
combinations are simply not allowed such as too weak gates driving too
much capacitance. Then there is the issue of static timing. Unlike with
flip flops, these circuits do not have pre-routed clock trees and so
won't even work unless some clock-tree synthesis is included in the flow
(unless we intend for people to hand create these.) All this and
probably much more I'm neglecting is required just to get to a logically
functional circuit.

Best regards,
Jason

-----Original Message-----
From: Stephen Williams [mailto:steve@icarus.com] 
Sent: Tuesday, February 25, 2003 3:31 PM
To: geda-user@seul.org; geda-dev@seul.org
Subject: Re: gEDA-user: putting it all together 



(This may be more like a subject for the geda-dev list.)

john_g@cibolo.com said:
> I have a combination of chip logic design and layout experience that 
> should let me make headway in this kind of project.  Would you please 
> tell us  more about the steps involved in making a icarus verilog code

> generator for the libraries supported by MOSIS?

The code generator API for Icarus Verilog is described in the
ivl_target.h header file, with sample code in the tgt-stub directory.
You can also look in the tgt-fpga directory for the FPGA code generator.
This should give you an idea of the complexity involved in doing a real
code generator.

The problem is two parts: the netlist format, and the cell library. EDIF
is the likely choice for a netlist format. The other choice is the cell
library to use. You can choose a standard library, or make up one of
your own. The task for the code generator is then to take the relatively
abstract devices that Icarus Verilog synthesizes, i.e. logic gates,
adders, subtractors, muxes, Flip-Flops, and so on, and generate EDIF
code to implement those from parts in your chosen cell library.

The fpga code generator for Xilinx Virtex, for example, generates a
chain of carry logic devices, which are primitives in Virtex parts, to
implement addition.

Electric can import EDIF files, by the way.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
steve at picturel.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."