Re: gEDA-user: putting it all together

[Stephen Williams <steve@icarus.com>]

(This may be more like a subject for the geda-dev list.)

john_g@cibolo.com said:
> I have a combination of chip logic design and layout experience that
> should let me make headway in this kind of project.  Would you please
> tell us  more about the steps involved in making a icarus verilog code
> generator for the libraries supported by MOSIS? 

The code generator API for Icarus Verilog is described in the
ivl_target.h header file, with sample code in the tgt-stub directory.
You can also look in the tgt-fpga directory for the FPGA code
generator. This should give you an idea of the complexity involved
in doing a real code generator.

The problem is two parts: the netlist format, and the cell library.
EDIF is the likely choice for a netlist format. The other choice is
the cell library to use. You can choose a standard library, or make
up one of your own. The task for the code generator is then to take
the relatively abstract devices that Icarus Verilog synthesizes, i.e.
logic gates, adders, subtractors, muxes, Flip-Flops, and so on,
and generate EDIF code to implement those from parts in your chosen
cell library.

The fpga code generator for Xilinx Virtex, for example, generates
a chain of carry logic devices, which are primitives in Virtex parts,
to implement addition.

Electric can import EDIF files, by the way.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
steve at picturel.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."