Re: gEDA-user: putting it all together

[John Griessen <john_g@cibolo.com>]

I have a combination of chip logic design and layout experience that
should let me make headway in this kind of project.  Would you please
tell us  more about the steps involved in making a icarus verilog code
generator for the libraries supported by MOSIS?

My assumptions:   MOSIS has standard cell library and custom capability
also.   For cells sized differently from the library, a new std. cell
would need to be made from scratch.  

1.  Once you have a collection of std. cells you need to make a range of
circuits, what you specify from the QUISC/Magic/Electric code-generator
viewpoint is a lookup list -- ((cellname, modulename),
(i01name,port1name), (io2name, port2name), (io3name, port3name),
(cell_ground, gnd), (cell_vdd or cell_vss, vcc)) -- to match up the
library components to your verilog module ports and module names...

2. No physical location of io's info needs to be part of such a code
generator, but power and ground and substrate would need to be explicit
in the structural verilog to get a good netlist to do layout versus
verilog verification or design rule checking.

John Griessen


On Sat, 2003-02-22 at 17:21, Stephen Williams wrote:
> It would be fairly nifty if someone would like to take the time to
> write a code generator for the libraries supported by MOSIS. Writing
> a code generator is easier then writing a synthesizer (the synthesis
> is already done) and even easier then writing the design for your
> chip; but harder then writing a simple set of printfs.