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gEDA-user: Heirarchical design (again)
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- Subject: gEDA-user: Heirarchical design (again)
- From: "Peter Brett" <peter.brett@xxxxxxxxxxx>
- Date: Thu, 10 Feb 2005 10:50:13 -0000
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- Delivery-date: Thu, 10 Feb 2005 05:53:14 -0500
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- Thread-index: AcUPXkyQJGPpRodLRomjkaxVeot1sA==
- Thread-topic: Heirarchical design (again)
Title: Heirarchical design (again)
Hey everyone,
I've got a two multi-component subcircuits that are repeated multiple times on my schematic, 23 and 68 times respectively.
I know how to create symbols with underlying schematics. My questions:
- Does the netlister know to recurse into the underlying schematics?
- What happens to refdes attributes?
Cheers,
Peter
--
System Display Group
Sharp Laboratories of Europe
http://www.sle.sharp.co.uk/research/sop/