gEDA-user: Icarus assertion failure

[Günter Dannoritzer <dannoritzer@xxxxxx>]

Hi,

I tried to simulate a code for a Manchester encoder from a Xilinx 
application note and Icarus cancels with an assertion failure. I could 
simulate the same code with modelsim.

I tried it with Icarus 0.8 and 0.8.1 on Linux. The code is added below 
and this are the commands I used to compile and start simulation:


$ iverilog -Wall -sme_tf -ome_tf.vvp me.v me_tf.v
me_tf.v:2: warning: Some modules have no timescale. This may cause
me_tf.v:2:        : confusing timing results.  Affected modules are:
me_tf.v:2:        :   -- module me declared here: me.v:21

$ vvp me_tf.vvp
ERROR (vpi_const.cc): vp->format: 6
Assertion failed: 0, file vpi_const.cc, line 130


Am I doing something wrong here? Is it a problem to the verilog code and 
modelsim just accepts it or is it a problem with Icarus?

Thanks for the help.

Guenter






// me.v ----------------------------------------------------------------

/******************************************************************************
*
*    File Name:  me.v
*      Version:  1.0
*         Date:  January 22, 2000
*        Model:  Manchester Encoder Chip
*
*      Company:  Xilinx
*
*
*   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
*                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY
*                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
*                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
*
*                Copyright (c) 2000 Xilinx, Inc.
*                All rights reserved
*
******************************************************************************/

module me (rst,clk16x,wrn,din,tbre,mdo) ;
input rst ;
input clk16x ;
input wrn ;
input [7:0] din ;
output tbre ;
output mdo ;

wire clk1x ;
reg clk1x_enable ;
wire clk1x_disable ;
reg [3:0] clkdiv ;
reg [3:0] no_bits_sent ;
wire mdo ;
reg tbre ;
reg [7:0] tsr ;
reg [7:0] tbr ;
reg parity ;
reg wrn1 ;
reg wrn2 ;

// Form 2 FF register for write pulse detection

always @(posedge rst or posedge clk16x)
if (rst)
begin
wrn2 <= 1'b1 ;
wrn1 <= 1'b1 ;
end
else
begin
wrn2 <= wrn1 ;
wrn1 <= wrn ;
end

// Enable clock when detect edge on write pulse

always @(posedge rst or posedge clk16x)
begin
if (rst)
clk1x_enable <= 1'b0 ;
else if (wrn1 == 1'b1 && wrn2 == 1'b0)
clk1x_enable <= 1'b1 ;
else if (no_bits_sent == 4'b1111)
clk1x_enable <= 1'b0 ;
end

// Generate Transmit Buffer Register Empty signal

always @(posedge rst or posedge clk16x)
begin
if (rst)
tbre <= 1'b1 ;
else if (wrn1 == 1'b1 && wrn2 == 1'b0)
tbre <= 1'b0 ;
else if (no_bits_sent == 4'b1010)
tbre <= 1'b1 ;
else
tbre <= 1'b0 ;
end

// Detect edge on write pulse to load transmit buffer

always @(posedge rst or posedge clk16x)
begin
if (rst)
tbr <= 8'h0 ;
else if (wrn1 == 1'b1 && wrn2 == 1'b0)
tbr <= din ;
end

// Increment clock

always @(posedge rst or posedge clk16x)
begin
if (rst)
clkdiv <= 4'b0000 ;
else if (clk1x_enable == 1'b1)
clkdiv <= clkdiv + 1 ;
end

assign clk1x = clkdiv[3] ;

// Load TSR from TBR, shift TSR

always @(posedge rst or posedge clk1x)
begin
if (rst)
tsr <= 8'h0 ;
else if (no_bits_sent == 4'b0001)
tsr <= tbr ;
else if (no_bits_sent >= 4'b0010 && no_bits_sent < 4'b1010)
begin
tsr[7:1] <= tsr[6:0] ;
tsr[0] <= 1'b0 ;
end
end

// Generate Manchester data from NRZ

assign mdo = tsr[7] ^ clk1x ;

// Generate parity

always @(posedge rst or posedge clk1x)
begin
if (rst)
parity <= 1'b0 ;
else
parity <= parity ^ tsr[7] ;
end

// Calculate number of bits sent

always @(posedge rst or posedge clk1x)
begin
if (rst)
no_bits_sent <= 4'b0000 ;
else if (clk1x_enable)
no_bits_sent <= no_bits_sent + 1 ;
// else if (no_bits_sent == 4'b1111)
else if (clk1x_disable)
no_bits_sent <= 4'b0000 ;
end

assign clk1x_disable = !clk1x_enable ;

endmodule



// me_tf.v-------------------------------------------------------------

`timescale 1 ns / 1 ns

module me_tf ;
reg [7:0] din ;
reg rst ;
reg clk ;
reg wr ;
wire mdo ;
wire ready ;
me u1 (rst,clk,wr,din,ready,mdo) ;
initial begin
rst = 1'b0 ;
clk = 1'b0 ;
din = 8'h0 ;
wr = 1'b0 ;
//u1.clk1x = 1'b0 ;
u1.clkdiv = 3'b0 ;
end
integer me_chann ;
initial begin
//me_chann = $fopen("me.rpt") ;
$timeformat(-9,,,5) ;
end
parameter clock_period = 10 ;
integer setup_time = clock_period/4 ;
always #(clock_period/2) clk = ~clk ;
initial begin
//$fdisplay(me_chann, "Verilog simulation of Manchester encoder\n\n:");
$display("Verilog simulation of Manchester encoder\n\n:");
//$shm_open("me.shm");
//$shm_probe("AS") ;
//$fmonitor(me_chann,"%ime=%t,rst=%b,wr=%b,me.clk=%b,din=%h,me.clkdiv=%b,mdo=%b,ready=%b",
//   $time,rst,wr,clk,u1.clk1x,din,u1.clkdiv,mdo,ready) ;
$monitor("time=%t,rst=%b,wr=%b,me.clk=%b,din=%h,me.clkdiv=%b,mdo=%b,ready=%b",
   $time,rst,wr,clk,u1.clk1x,din,u1.clkdiv,mdo,ready) ;
#5 rst = 1'b1;
#15 rst = 1'b0 ;
#(3 * clock_period - setup_time) din = 8'hff ;
#(1 * clock_period) wr = 1'b1 ;
#(1 * clock_period) wr = 1'b0 ;
#(20 * clock_period) din = 8'haa ;
#(1 * clock_period) wr = 1'b1 ;
#(1 * clock_period) wr = 1'b0 ;
#(20 * clock_period) din = 8'h00 ;
#(1 * clock_period) wr = 1'b1 ;
#(1 * clock_period) wr = 1'b0 ;
#(20 * clock_period) din = 8'hf0 ;
#(1 * clock_period) wr = 1'b1 ;
#(1 * clock_period) wr = 1'b0 ;
#(20 * clock_period) din = 8'h0f ;
#(1 * clock_period) wr = 1'b1 ;
#(1 * clock_period) wr = 1'b0 ;
#(100 * clock_period) ;
//$fdisplay (me_chann,"\nSimulation of Manchester encoder complete.");
$display ("\nSimulation of Manchester encoder complete.");
$finish ;
end
endmodule