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gEDA-user: how to make DRC ignore "outline" layer?

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Subject: gEDA-user: how to make DRC ignore "outline" layer?
From: Mark Rages <markrages@xxxxxxxxx>
Date: Wed, 10 Feb 2010 16:22:57 -0600
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Hi, I'm making a layout with castellated vias on the edge.  so these
vias intersect the outline layer and pcb thinks they are all shorted
together when I press "o".

Any way around this?  I thought the magic was the name "outline".

Regards,
Mark
markrages@gmail
-- 
Mark Rages, Engineer
Midwest Telecine LLC
markrages@xxxxxxxxxxxxxxxxxxx


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