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gEDA-user: Re: PCB

Don't make an easy problem hard.

Look at the 7400-1.sym in the lib. It is a quad nand gate in a dip14 package.
Create a new 7400-1s.sym that is identical except that that each gate has it's
input pins swapped.

Now create a new attribute called SWAP in both syms. In 7400-1.sym you set SWAP
to 7400-1s.sym and in 7400-1s.sym you set it to 7400-1.sym.

To preform a swap now all you need to do is replace the symbol name in the schematic
with the value in it's SWAP attribute. You can do that in a gschem menu pick of from a
back anno program. Redraw the schematic after the swap and your inputs will be swapped.

You can do the same thing to DEMORGAN gates. Just make sure that the pins hot spots
never move between symbols and your all set.

Only problem is that this schem runs out of steam real fast once you get more than two
input pins on a gate.

John Eaton















Stuart Brorson wrote:

Am 02.01.2005 um 07:11 schrieb M. P. Dickens:


If you take the time to learn how to use pcb, there is very
little you can't do with it (Or at least, that's been my
experience).


Gate- and Pin-Swapping?



Along with backannotation to gschem.

I say this not to slam PCB, BTW. Eventually, I envision having a
gEDA program "gbackanno" which would take a .pcb file & backannotate
it to gschem. 

I've talked to Ales about this at one of our Free Dog meetings; we
both agree that it would be a great thing, and represents a missing
link in the gEDA tool chain.  First, however, the way in which gEDA's
attributes are architected would need to change.  Specifically:  As
currently set up, pin attributes -- such as pinseq and pinno -- are
attached to the pin itself, and are not held at the schematic
level.  Here's an example cap. instantiated at schematic level:

C 70200 44500 1 0 0 capacitor-1.sym
{
T 70400 45000 5 10 1 1 0 0 1
refdes=C1
T 70200 44500 5 10 1 1 0 0 1
value=1nF
T 70200 44500 5 10 0 0 0 0 1
footprint=1206
}

In the cap-1.sym file, you find the pins & pin attributes:

v 20031231 1
P 0 200 200 200 1 0 0
{
T 100 250 5 6 0 1 0 0 1
pinnumber=1
T 100 50 5 8 0 0 0 0 1
pinseq=1
}
P 900 200 700 200 1 0 0
{
T 700 250 5 6 0 1 0 0 1
pinnumber=2
T 700 50 5 8 0 0 0 0 1
pinseq=2
}
L 400 400 400 0 3 0 0 0 -1 -1
L 500 400 500 0 3 0 0 0 -1 -1
L 700 200 500 200 3 0 0 0 -1 -1
L 400 200 200 200 3 0 0 0 -1 -1
T 1000 300 5 8 0 0 0 0 1
device=CAPACITOR
T 100 400 5 10 1 1 0 0 1
refdes=C?
T 600 400 5 10 1 1 0 0 1
value=1n
T 1000 -100 5 8 0 1 0 0 1
description=linear poly0 / poly1 capacitor
T 600 250 5 8 1 1 0 0 1
model-name=cpolylin

The pinno and pinseq info held in the .sym file becomes part
of the netlist when gnetlist reads in the .sym file and attaches the
pins it finds to the nets which touch them. Therefore, there is no
way to modify this info by modifying the schematic or the schematic
file. 

To make backannotation work, the backannotated pin attributes need to
live at the schematic level since you backanno the .pcb file to the
.sch file.  Accordingly, to enable backannotation, one needs to modify
the libgeda parsing routines so that symbol-level pin attributes can
be overridden by pins and pin attributes attached at the schematic
level.  This seems to me to be a fairly involved modification to the
way in which gEDA works.

I'm thinking about doing this at some point in the bright and distant
future.  It would be a good thing, because it would immediately enable
you to use gattrib to do pin swaps -- sort of a poor man's
backannotation.  However, since there is great interest in hacking gEDA
on this list, I throw this one out there to see if anybody else feels
motivated to try it.  If any newbie wants to get his feet wet with
gEDA's internals, this is a great place to start, and I would be happy
to supply him with any and all info I have learned from hacking
libgeda.  Barring that, I will probably do this myself over the coming
months & years . . . .

Stuart