[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]

gEDA-user: Register enables in Icarus



Say I want to make a clocked, enabled register. This would simply be the following in behavioral verilog:

    always @(posedge clk) begin
    if (en) begin
      Q <= D;
    end
    end

That verilog will work with most tools, but it seems to me that if I want to use Icarus synthesis, I have to change the code to the following:

    always @(posedge clk) begin
    if (en) begin
      Q <= D;
    end else begin
      Q <= Q;
    end
    end

However, this doesn't really describe a register with an enable signal. Is this making any sense?
Thanks for any insights.
-d