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Re: gEDA-user: Register enables in Icarus

David Howland wrote:
Say I want to make a clocked, enabled register. This would simply be the following in behavioral verilog:

    always @(posedge clk) begin
    if (en) begin
      Q <= D;
    end
    end


That works for me. It simulates fine, and it synthesizes too. I think
there is something more to your problem then this. I'm using 0.8.

--
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
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