Re: gEDA-user: Register enables in Icarus

[Charles Lepple <clepple@xxxxxxxxx>]

On Thu, 06 Jan 2005 16:09:03 -0500, Thomas A.D. Riley
<tom.riley@xxxxxxxxxxxxxxxxx> wrote:
> The "always @(posedge clk or en):
> begin simulates in Icarus but won't synthesize in some commercial tools.
>  So what to do depends on what you want. 
  
sorry for the confusion-- that doesn't synthesize in iverilog, either.
I was mixing that up with asynchronous resets, which I'm pretty sure
you do have to put in the sensitivity list (with an edge spec). I'm
going to go crawl under a rock now.

Before I do, let me throw this out: what's wrong with the first piece
of code that David posted? Here's the netlist generated by 'iverilog
-S':

DESIGN TIME PRECISION: 10e0
SCOPES:
main module <main>
    timescale = 10e0 / 10e0
    wire: D[1] input (eref=0, lref=0) scope=main #(0,0,0) init=z (z)
        [0]: 0x817b4c8 D
    wire: Q[1] output (eref=0, lref=0) scope=main #(0,0,0) init=x (x)
        [0]: 0x817ae30 Q
    wire: clk[1] input (eref=0, lref=0) scope=main #(0,0,0) init=z (z)
        [0]: 0x817a8a8 clk
    wire: en[1] input (eref=0, lref=0) scope=main #(0,0,0) init=z (z)
        [0]: 0x817aed8 en
ELABORATED NODES:
LPM_FF: _s2 scope=main aset_value='d0
    0 Clock<0> I (strong0 strong1): 0x817a8a8 clk
    1 Enable<0> I (strong0 strong1): 0x817aed8 en
    2 Aload<0> I (strong0 strong1):
    3 Aset<0> I (strong0 strong1):
    4 Aclr<0> I (strong0 strong1):
    5 Sload<0> I (strong0 strong1):
    6 Sset<0> I (strong0 strong1):
    7 Sclr<0> I (strong0 strong1):
    8 Data<0> I (strong0 strong1): 0x817b4c8 D
    9 Q<0> O (strong0 strong1): 0x817ae30 Q
    LPM_FFType = ""DFF""
ELABORATED PROCESSES:

... which I take to be a D flip-flop with 'en' tied to the (clock)
enable. Is that not reflected in the simulation?

-- 
- Charles Lepple