Re: gEDA-user: Vias with zero clearance in PCB?

[DJ Delorie <dj@xxxxxxxxxxx>]

> > thermal(1,2,3)  - thermals on layers 1, 2, and 3.
> 
> What I miss are thermals for pads too.

Hmmm... modifiers for thermals  (i.e. thermal(1L,2+))

L R U D = single trace in that direction (combinable, like UL or DR)
+ x     = four traces in cross configuration; horiz/vert or diags
| - / \ = two traces in that direction (| and - useful for pads)
*       = eight traces for high current
A       = automatic selection       

Not that I plan on *supporting* that.  Just thinking out loud.  We'd
need an eight bit mask for each thermal on each layer, plus an enum
for the "type" of thermal (none, manual thermal, auto thermal, solid)

> I know it's hard to code.

Yup :-P

But if we did that, it would get rid of the need for the thermal
modifiers.  They'd all be automatic, me thinks, and if you want
otherwise, you draw in traces yourself.