Re: gEDA-user: G in PCB

[DJ Delorie <dj@xxxxxxxxxxx>]

When I worked at Data General, the CAD system they used had an
optimizer that did all that for you.  They'd run the traces manually
(I don't recall if they had an autorouter back then) and then run
various optimizers.  One of them was called "PULLIT" and gave you
traces like that example.  The idea, at the time, was signal quality.

> What I didnt understood is if you made that board writing in emacs a
> .pcb file or a .grb file? Pcb accepts semi-arc in his syntax?

I used emacs on the .pcb file.  You can tell, below, because the lines
aren't all in a group.  Yes, PCB fully supports semi-arcs, you just
can't create them with the GUI.

# release: pcb-bin 1.99q
# date:    Thu Jan  5 13:58:27 2006
# user:    dj (DJ Delorie)
# host:    envy.delorie.com

PCB["" 100000 100000]

Grid[500.00000000 0 0 0]
Cursor[0 0 0.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000]
Flags(0x0000000000001c40)
Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]

Via[40000 10000 6000 2000 0 2800 "" ""]
Via[40000 30000 6000 2000 0 2800 "" ""]
Via[40000 50000 6000 2000 0 2800 "" ""]
Via[30000 54500 6000 2000 0 2800 "" ""]
Layer(1 "component")
(
	Line[40000 10000 35615 28987 1000 2000 "clearline"]
	Line[35990 32042 44009 47957 1000 2000 "clearline"]
	Line[40000 50000 30000 50000 1000 2000 "clearline"]
	Line[30000 54500 40000 54500 1000 2000 "clearline"]
	Arc[40000 30000 4500 4500 1000 2000 -13 40 "clearline"]
	Arc[40000 50000 4500 4500 1000 2000 90 117 "clearline"]
	Arc[40000 50000 6500 6500 1000 2000 114 84 "clearline"]
	Arc[30000 54500 4500 4500 1000 2000 -90 204 "clearline"]
	Line[31830 58610 42643 55938 1000 2000 "clearline"]
	Line[46181 47991 40000 30000 1000 2000 "clearline"]
)
Layer(2 "solder")
(
)
Layer(3 "GND")
(
)
Layer(4 "power")
(
)
Layer(5 "signal1")
(
)
Layer(6 "signal2")
(
)
Layer(7 "signal3")
(
)
Layer(8 "signal4")
(
)
Layer(9 "silk")
(
)
Layer(10 "silk")
(
)