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Re: gEDA-user: Hierarchical Verilog design with BUS

Paul Tan wrote:
> Hi All,
> 
> Attached is a package which contains a Hierarchy
> source report script.

Thanks Paul,

I'm just now studying the verilog-ams manual and a gnetlist patch
for generating verilog with gnucap in mind.  At least in spare moments...  I'm sure your script will be a help.

John

-- 
Ecosensory   Austin TX


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