Re: gEDA-user: Hurray for gEDA!

[John Doty <jpd@xxxxxxxxx>]

On Jan 24, 2009, at 6:33 PM, Ales Hvezda wrote:

>
> Hi JohnD,
>
> [snip]
>> Last night I delivered the schematic design and netlist for a data
>> acquisition board for the TESS space mission. 1200 components, but
>> the design is only seven schematics and three connector pin list
>
> 	Neat!
>
> 	Out of curiousity, how do you verify that the generated netlist
> matches the schematic?

Visual spot checks. I don't have any practical way to do a complete  
job here, but I try to sample enough different kinds of connections  
(like across multiple hierarchy levels) to detect any pattern of  
error. On a previous design I discovered by this method that  
connecting higher level nets through a net at a lower level does not  
work, so I don't do that (I suppose I should put in a bug report).

The layout guy actually has pretty good knowledge of the circuit, so  
he acts as a checker also.

And then, in a few weeks, I plug it in and watch for smoke ;-). I  
will be much happier to debug a board made with 0603's than 0402's...

Generally, I find the rate of errors due to my own mistakes is much  
higher than the rate due to bugs in the tools, so minimizing the  
design files and automating their expansion into a complete design is  
a good thing. I'm a lousy clerk.

John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd@xxxxxxxxx




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