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Re: gEDA-user: Collaborative Development of Boards

On Mon, 2011-01-17 at 21:29 +0100, Kai-Martin Knaak wrote:
> Peter Clifton wrote:
> > What about extracting the topology of the tracks (probably using /
> > refactoring some code from the topological auto-router).

> Isn't this what gnetlist does?

No - we are talking cross purposes I think. gnetlist produces a netlist
from a schematic.

With regards the PCB, I was thinking more of producing an output which
described the _topology_ of the wiring.

That is, describing relative to other wiring / obstacles, where various
tracks are, but without getting into the minutiae of which XY
coordinates each segment of track occupies.

Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)

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