RE: gEDA-user: mixed 5.0/3.3/1.8 V designs?

[Alex Perry <alex.perry@qm.com>]

Personally, I never use logic symbols (for board design) that
don't have explicit power and ground connections.  There are
three reasons forcing this approach:
(1) mixed signal (analog and digital) _have_ to be segmented
(2) any non-trivial digital design will use multiple voltages
(3) any high speed design will use rail management for EMC
As commented before, ASIC design has the same problems.

Although trivial designs and the special cases of FPGA
schematics don't have those problems, if you want to be
able to migrate chunks of simple design into a complex
design, it is a good idea to always use the power pins.
In many cases, complex designs that have power errors 
are the result of simple subdesigns (without power pins)
being incorrectly integrated into a more complex project.

When extracting a board design for verilog simulation,
having the power pins present allows the chip model to
correctly implement the behavior of protection diodes
and therefore give the effect of disconnected power pins.
This is especially valuable when doing power management.

> whats
> the way to mix different digital supply voltages in the 
> same design and be
> fairly certain of not having the wrong ones connected?

The traditional way is to name the entire power netlist pair
as "VCC" and "GND", but to do the PCB with copper pours
instead of simple planes.  This lets you break the plane
into disconnected pieces that are only logically related.
You lose the benefit of netlist checking by doing this,
so I prefer the route above.  An alternative is to use
a little script that looks for suffixes on the part name
of "_3p3" and similar ... then renames the nets attached
to the pins appropriately.  If you do this, be _sure_ to
annotate the schematic so that subsequent engineers don't
get confused by the fact that schematic and PCB mismatch.

PS.

Some schematic packages allow you to assign default net
names to pins (when they are not connected in schematic).
It appears convenient, for dealing with this situation,
but I've heard that it creates more design mistakes.