gEDA-user: Multiple modules in source

["CN" <mis4@xxxxxxxxxxx>]

A very basic newbie question. Is ivl supposed to produce synthesis code for multiple modules in one file?  If I run the following sorce with -tfpga -parch=virtex v0.8.1

`timescale 1ns / 1ps
module add4(AAA, BBB,  OOO);
    output [3:0]OOO;
    input [3:0]AAA;
    input  [3:0]BBB;
    
    assign OOO =   AAA + BBB;
endmodule

module sub4( CCC, DDD, PPP);
    output [3:0]PPP;
    input [3:0]CCC;
    input  [3:0]DDD;

    assign PPP =   CCC - DDD;
endmodule

I only see the output generated for the first module.  What am I doing wrong?

Cordially, CN