Re: gEDA-user: Multiple modules in source

["CN" <mis4@xxxxxxxxxxx>]

Charles,


Thank you for that quick pointer.  I added a root module and instantiated the other two modules in it, and in synthesis everything now shows up correctly.  Thanks again.


Cordially, CN



On Fri, 15 Jul 2005 15:56:43 -0400, Charles Lepple wrote:


On 7/15/05, CN <mis4@xxxxxxxxxxx> wrote:

> A very basic newbie question. Is ivl supposed to produce synthesis code for multiple

> modules in one file?  If I run the following sorce with -tfpga -parch=virtex v0.8.1


I think you want the '-s' option. Check the manpage and search for

'-s', and it explains how it chooses the "root module".


When synthesizing a real-world design with iverilog, you typically

only have one root module, and other modules are used for simulation,

etc. See examples/sqrt-virtex.v for more information.


-- 

- Charles Lepple