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Re: gEDA-user: Gnetlist Verilog

Hi,

I assume you are talking about these messages (from an old version of gschem / gnetlist, but the warning you are getting should be the same, I have not updated the netlister since that time):
-----
[mjarabek@scotty tmp]$ gnetlist -g verilog -o test.v test.sch
gEDA/gnetlist version 20040111
gEDA/gnetlist comes with ABSOLUTELY NO WARRANTY; see COPYING for more details.
This is free software, and you are welcome to redistribute it under certain
conditions; please see the COPYING file for more details.

Loading schematic [test.sch]
Warning: `3' is not likely a valid Verilog identifier
Warning: `2' is not likely a valid Verilog identifier
Warning: `5' is not likely a valid Verilog identifier
Warning: `1' is not likely a valid Verilog identifier
Warning: `4' is not likely a valid Verilog identifier
Warning: `6' is not likely a valid Verilog identifier
Warning: `14' is not likely a valid Verilog identifier
Warning: `7' is not likely a valid Verilog identifier
Warning: `3' is not likely a valid Verilog identifier
Warning: `2' is not likely a valid Verilog identifier
Warning: `1' is not likely a valid Verilog identifier
Warning: `14' is not likely a valid Verilog identifier
Warning: `7' is not likely a valid Verilog identifier
[mjarabek@scotty tmp]$
-----

These are warnings, and the output Verilog code will have escape sequences around the offending identifiers to protect them. You can ignore these safely. The best thing to do is to label the pins on the sub-blocks with valid verilog identifiers. Adjust the `pinnumber' attribute on the symbol to have a verilog name on it, and these warnings will go away.

Keep in mind that if you chose to ignore them your simulation model for the 7400 and 7474 will have to have module ports declared with names that are the pin numbers, and these have to be escaped. Consult your local Verilog reference for how to do this safely. You will also have to add an unatached atrribute for the module name to your schematic. Follow the instructions in README.verilog in the gnetlist/docs directory.

Hope this helps.

Mike

User Tomdean wrote:

How do I generate verilog with gnetlist?  I have a simple schematic
with a 7400 and a 7474, below.

I used gnetlist -g verilog -o test.vl test.sch.  Gnetlist complains of
pin numbers not being valid identifiers.

I made symbols with pintype CHIPIN, CHIPOUT, etc., naming these
7400-vl.sym and 7474-vl.sym

tomdean

v 20060123 1
C 18900 54700 1 0 0 7400-vl.sym
{
T 19200 55600 5 10 1 1 0 0 1
refdes=U1
}
C 22400 54300 1 0 0 7474-vl.sym
{
T 23700 56300 5 10 1 1 0 6 1
refdes=U2
}
N 20200 55200 21400 55200 4
N 21400 55200 21400 55900 4
N 21400 55900 22400 55900 4
{
T 21700 55900 5 10 1 1 0 0 1
netname=Q1
}
N 22400 54900 22400 54400 4
N 22400 54400 18800 54400 4
{
T 18800 54400 5 10 1 1 0 0 1
netname=CLK
}
N 18800 55000 18900 55000 4
{
T 18800 55000 5 10 1 1 0 0 1
netname=B
}
N 18800 55400 18900 55400 4
{
T 19000 54700 5 10 1 1 0 0 1
netname=A
T 18800 55400 5 10 1 1 0 0 1
netname=A
}
N 24000 55900 24200 55900 4
{
T 24100 55900 5 10 1 1 0 0 1
netname=Q
}
N 24000 54900 24200 54900 4
{
T 24200 54900 5 10 1 1 0 0 1
netname=NOTQ
}
N 23200 56500 23200 56600 4
N 23200 56600 18800 56600 4
{
T 18900 56600 5 10 1 1 0 0 1
netname=CLR
}
N 23200 54300 23200 54000 4
N 23200 54000 18800 54000 4
{
T 18900 54000 5 10 1 1 0 0 1
netname=PRE
}


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--
--------------------------------------------------
                             Mike Jarabek
                               FPGA/ASIC Designer
http://www.istop.com/~mjarabek
--------------------------------------------------





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