Re: gEDA-user: Problems with subnets containing short-circuits

[Mike Jarabek <mjarabek@xxxxxxxxx>]

So,

   It's a short circuit between two pins of a sub-block that is not 
netlisted correctly?

  Can you craft a small example that does not work and post it?

  Does this only happen in the spice netlister?

Mike

Arvid Rosén wrote:

> Stuart Brorson wrote:
>
> > Just out of curiosity, why would you want to have two nets which
> > connect to nothing other than each other?
> >
> > Before we label it a bug, what is the goal of this construct? 
> > Stuart
> >   
>
> Hi Stuart!
> That's a good question. The construct itself is quite pointless. 
> However, I was working on a quite complex design with two 
> filter-subcircuits. I wanted to test some aspects of my circuit, so I 
> shorted the first filter just to bypass it, which resulted in an open 
> circuit instead of a bypass! That is quite annoying, don't you think?
> The possibility to bypassing stuff is always important when debugging.
>
> Cheers
> Arvid
>
> >  
> >
> > > John Luciani wrote:
> > >    
> > >
> > > > On 7/20/06, Arvid Ros=E9n <arvid@xxxxxxxxxx> wrote:
> > > >      
> > > >
> > > > > However, I also tried to make a 2-pin subnet containing only a
> > > > > short-circuit. This connection was completely ignored by gnetlist!!
> > > > >
> > > > > Could someone confirm this?
> > > > >         
> > > >
> > > > You are correct. If you have two nets that only connect to each other
> > > > the connection does not show up in the netlist.
> > > >
> > > > I get around this by connecting one of the nets to a component.
> > > >
> > > > (* jcl *)
> > > >
> > > >       
> > >
> > > Ok, thanks!
> > > Shouldn't that be considered as a pretty severe bug? I am new here,=20
> > > maybe it's already reported.
> > >
> > > /Arvid
> > >
> > > --=20
> > > Arvid Ros=E9n
> > > Softube AB
> > > Teknikringen 7
> > > S-583 30 Link=F6ping
> > > Sweden
> > > Phone: (+46) 13 21 16 23
> > > Mobile: (+46) 73 25 12 34 7
> > > Mail: arvid@xxxxxxxxxx
> > > URL: www.softube.se
> > >
> > >
> > >
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> > >
> > >     
> >
> >
> >
> >
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> >   

--
--------------------------------------------------
                             Mike Jarabek
                               FPGA/ASIC Designer
http://www.istop.com/~mjarabek
--------------------------------------------------





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