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Re: gEDA-user: Re: PCB + Loadint Net

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Subject: Re: gEDA-user: Re: PCB + Loadint Net
From: DJ Delorie <dj@xxxxxxxxxxx>
Date: Wed, 26 Jul 2006 14:01:16 -0400
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References: <200607191653.k6JGrEdX002842@asus.tddhome> <e9rr5t$55d$1@sea.gmane.org> <e9rt9o$94p$1@sea.gmane.org> <200607220212.k6M2CLLv050229@asus.tddhome> <200607220216.k6M2G6Kk006490@envy.delorie.com> <200607220241.k6M2fs9W050373@asus.tddhome> <200607220244.k6M2iDGF007192@envy.delorie.com> <200607261704.k6QH4a0d031939@asus.tddhome> <608bfe540607261018i323d454tb866663d9120e710@mail.gmail.com> <200607261747.k6QHleQ0048342@asus.tddhome> <608bfe540607261058o1012a5bai879b59ccc413e37d@mail.gmail.com>
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I've reproduced this with HID; it seems that netlists loaded from the
File menu aren't enabled by default, but netlists loaded with the .pcb
are.  For example, after loading the netlist, save the pcb and load it
again.  Presto!  Optimize rats works.

Working on it . . .


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- Re: gEDA-user: Re: PCB + Loadint Net
  - From: User Tomdean

References:
- gEDA-user: Gnetlist Verilog
  - From: User Tomdean
- gEDA-user: Re: PCB + Loadint Net
  - From: kai-martin knaak
- gEDA-user: Re: PCB + Loadint Net
  - From: kai-martin knaak
- Re: gEDA-user: Re: PCB + Loadint Net
  - From: User Tomdean
- Re: gEDA-user: Re: PCB + Loadint Net
  - From: DJ Delorie
- Re: gEDA-user: Re: PCB + Loadint Net
  - From: User Tomdean
- Re: gEDA-user: Re: PCB + Loadint Net
  - From: DJ Delorie
- Re: gEDA-user: Re: PCB + Loadint Net
  - From: User Tomdean
- Re: gEDA-user: Re: PCB + Loadint Net
  - From: John Luciani
- Re: gEDA-user: Re: PCB + Loadint Net
  - From: User Tomdean
- Re: gEDA-user: Re: PCB + Loadint Net
  - From: John Luciani

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