gEDA-user: Icarus Verilog Release 0.8.5

[Stephen Williams <steve@xxxxxxxxxx>]

This is the first time I've used git to spit out a release. I have
to say, using the git-gui to scan the commits really puts the
summary of changes right there in my face. Writing release notes
is tons easier this way.

Anyhow, the release tarball is here:

<ftp://ftp.icarus.com/pub/eda/verilog/v0.8/verilog-0.8.5.tar.gz>
<ftp://ftp.icarus.com/pub/eda/verilog/v0.8/verilog-0.8.5.txt>

It's also tagged as v0_8_5 on the v0_8-devel branch within git.
And, I've made a srpm and x86_64 binary rpm.

Release Notes for Icarus Verilog 0.8.5

This is mostly a bug-fix release for the 0.8 stable branch.

* Fix assertions from unary operators with certain operand widths.

* Fix incorrect comparison results when in certain cases comparing two
signed negative integers.

* Latch synthesis has been added to the core synthesizer

* Add nand gate support to the edif code generator

* Minor compile time errors/warnings
* Improved messages from the configure script


-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."


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