gEDA-user: Icarus: Synthesize Verilog to Verilog

[Philipp Klaus Krause <pkk@xxxxxxx>]

Is it possible to use Icarus to simplify Verilog code?
I would like to use Berkeley VL2MV/VIS and SIS or ABC, however these
tools understand only a very limited subset to verilog. Can Icarus be
used to synthesize Verilog into a simplified Verilog? SIS and ABC seem
to be a good tools for optimization and can do some technology mapping.

The Verilog subset understood by VL2MV (which I use to convert Verilog
to BLIF, which is used by SIS and ABC) is a bit limited, e.g. no
functions, no multiplication or division. Details can be found in
http://www.zemris.fer.hr/labosi/osstr/doc/vl2mv.pdf
If Icarus could "synthesize" Verilog to a simplified Verilog usable by
VL2MV, this would lead e.g. to an improved open flow for ASIC design.

Philipp

P.S.: I tried building Icarus 0.9.1 with the verilog target (moving the
tgt-verilog directory from NOUSED to SUBDIRS in Makefile.in), but still
get an error message:

krauseph@kauai:~/ftc_dec$ /usr/local/scratch/usr2/bin/iverilog -o test-v
-tverilog ftc_dec.v
ERROR: Unable to read config file:
/usr/local/scratch/usr2/lib/ivl/verilog.conf
: error: target_design entry point is missing.
error: Code generator failure: -2



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