Re: gEDA-user: Timing in Icarus Verilog not working

[Philipp Klaus Krause <pkk@xxxxxxx>]

I now found a working alternative:

module and2 (A, B, O);
input  A ;
input  B ;
output O ;

   and #(3.62329, 4.98817) (O, A, B);

endmodule

Philipp


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