gEDA-user: Timing in Icarus Verilog not working

[Philipp Klaus Krause <pkk@xxxxxxx>]

I want to model gate delays, but everything happens without delay.
Icarus gives no errors messages or warnings. I used gates such as the
following:

module and2 (A, B, O);
input  A ;
input  B ;
output O ;

   and  (O, A, B);

   specify
     // delay parameters
     specparam
       rise = 3.62329:3.62329:3.62329,
       fall = 4.98817:4.98817:4.98817;

     // path delays
     (A *> O) = (rise, fall);
     (B *> O) = (rise, fall);

   endspecify

endmodule

Philipp


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