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gEDA-user: Timing simulation in Icarus Verilog

I would like to use Icarus Verilog for timing simulation. Is this possible?

I would have delay times for gates from another source (probably spice
simulation). I'd like to generate a gate netlist using Icarus and then
simulate it using the delay times. I sthis possible? If no, what would
be the alternatives?

Philipp



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