gEDA-user: Strange behavior from Icarus Verilog

[Patrick Doyle <wpdster@xxxxxxxxx>]

When I run the following code in Icarus Verilog:

`define Tnom 140e-9
`define Rele 2e3
`define Cele 0.3e-6
`define Vdd1p8 1.7
`define DrvIstep 1e-6
`define ADCScale (1024/`Vdd1p8*`DrvIstep)

module check_this();

integer pulse_dur = 15;
integer delta3 = 1;
integer drvw1 = -20;
initial begin
 $display("%f,%f,%f,%0d",
	         drvw1*(`Rele - (pulse_dur-delta3)*216*`Tnom/`Cele)*`ADCScale,
	        -drvw1*(`Rele - (pulse_dur-delta3)*216*`Tnom/`Cele)*`ADCScale,
	    -1.0*drvw1*(`Rele - (pulse_dur-delta3)*216*`Tnom/`Cele)*`ADCScale,
	  $rtoi(-drvw1*(`Rele - (pulse_dur-delta3)*216*`Tnom/`Cele)*`ADCScale));
  $finish;
end
endmodule

 get the following output:

-24.094118, 0.000000, 24.094118, 7

I think that the 4 numbers should be identical.  It is possible that
there is some funny conversion rule, or undefined behavior in the
Verilog spec that might result in the second output being zero, but I
don't understand why I get 24 for the 1st & 3rd output and 7 for the
final output (which is much closer to what I would expect).

So I'm asking for a couple of favors...
1) Can somebody else try this code and see if you get the same sort of results?
I compile and run it with:

$ iverilog -Wall -I.. -y..  -o check_this.vvp check_this.v
$ vvp check_this.vvp

$ iverilog -V
vvp.tgt: Icarus Verilog VVP Code Generator 0.10.0 (devel)
(s20090923-223-g9fbb12d)
$ vvp -V
Icarus Verilog runtime version 0.10.0 (devel) (s20090923-223-g9fbb12d)

I'm running on a Mac(book).

2) If this behavior is to be expected, could somebody explain why?

3) If it's not expected, I'd be glad to take a crack at figuring out
what went wrong where, or at least to post this to the buglist.  I'd
like to be able to do more to give back, so I'm willing to poke
around.

Thank you.

--wpd


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