Re: gEDA-user: conditional assign gets compile error

[Matthew Ballance <ballance@ballance.dhs.org>]

Hi,
   Looks like this might be a bug. Apparently, the bug is with the usage
of the decimal radix with 'z'. If you change to using hex (64'hz) or
binary (64'bz), everything works okay.
   Okay, here are the things that I've tested (just for everyone's
interest)

- 64'dz
	- Fails
- 64'dx
	- Fails
- 64'd10
	- Works
- 64'hz
	- Works
- 64'bz
	- Works

-Matt

-
On Tue, 2002-06-18 at 07:39, Lonnie L Gliem wrote:
> I am using iverilog v0_6_1.
> 
> When it encounters the following conditional assign.
> 
>   assign DR_DATA = DR_READ ? 64'dz
>                            i                              : DR_DATA_REG;
> 
> I get the following error:
> 
> PARSING INPUT ...
> 151: unmatched character (')
> drv_iv.v:151: parse error
> drv_iv.v:151: error: syntax error in continuous assignment
> make: *** [test_iver] Error 2
> 
> This works on vcs but not here anyone know why.
> 
> Lonnie
> 
>