gEDA-user: Icarus Verilog: Asynchronous if statement is missing the else clause

["CN" <mis4@xxxxxxxxxxx>]

I am very new here. So please guide me if I am off...

I tried the following on iv 0.8 (winxp):

----------
module latch1 (clk, d, q);
input clk, d;
output q;
reg q;
                 
always @ (clk or d) begin
   if (clk == 1'b1) begin
      q = d;
   end 
end
                 
endmodule
----------

With the command line
iverilog -tfpga -parch=virtex latch1a.v

get the errors:
latch1a.v:7: error: Asynchronous if statement is missing the else clause.
latch1a.v:6: internal error: is_asynchronous does not match sync_async results.

Is this to be expected?  What am I doing wrong?


Then I changed the source to:
-------
module latch1 (clk, d, q);
input clk, d;
output q;
reg q;
                 
always @ (clk or d) begin
   if (clk == 1'b1) begin
      q = d;
   end 
   else begin
      q = q;
   end
end
                 
endmodule
-------

Now I get the error
latch1b.v:6: warning: Process not synthesized.
fpga target: unsynthesized behavioral code

Any suggestions?

Cordially,
CN