Re: gEDA-user: Getting symbols from ASIC libraries into gschem: one approach

[Jeff Trull <jetrull@xxxxxxxxxxxxx>]

On Tuesday 12 June 2007 15:24:11 John Griessen wrote:
> Jeff Trull wrote:
> > If by "fancy" you mean "containing arcs", it's quite a few -
> > or/nor,xor/xnor, and all the ao/oa combinations with their different
> > sizes.
>
> Oh, yes.  It's been awhile since I've dealt with ASIC cells.   One forgets
> 5 input NORs exist as design elements when making boards...  So you want
> all the NOR and NAND gate symbols we are used to for making schematics. 
> Once your customer has gschem schematics, will they keep those as their top
> level docs, or pipe it back into Cadence/Synopsys somehow for "pre tapeout"
>  double checking, LVS, timing, test program writing?

They serve a few different purposes:

1) timing prototyping/simulation
2) documentation
3) design entry

For the last one, the schematics are intended to become modules within a major 
EDA vendor's flow, so part of my job is to figure out how to cleanly merge 
them in with blocks that are synthesized.  This semi-custom design flow will 
be used for timing or power critical blocks and the rest of the chip will be 
designed primarily at the RTL level.

>
> John Griessen
>
>
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