Re: gEDA-user: [Icarus Verilog] Unable to synthesize synchronous process

[Larry Doolittle <ldoolitt@xxxxxxxxxxxxxxx>]

On Tue, Jun 03, 2008 at 02:09:34AM +0400, wookiee@xxxxxxxxxxxxxxxxxxxx wrote:
> I've started with free Xilinx ISE, but now i'm trying to do my best to
> take part in icarus verilog community.

Welcome!

> iverilog -tfpga test.v
> test.v:7: sorry: Forgot to implement NetCondit::synth_sync
> test.v:6: error: Unable to synthesize synchronous process.
> 2 error(s) in post-elaboration processing.
> 
> Where is my mistake? What should i read to understand my problem?

I guess you use the devel tree.  If you really want to synthesize,
you should use 0.8.6 instead.  If you want to help port the synthesizer
from 0.8.6 to current devel, read the source and start hacking!

Synthesis in Icarus is historically weak compared to commercial
tools.  Steve mentioned to me privately that he might find time
to think about this again in s23%%43qaazz [carrier lost]


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