Re: gEDA-user: [Icarus Verilog] Unable to synthesize synchronous process

[Stephen Williams <steve@xxxxxxxxxx>]

wookiee-5fEA2WC4m+RvKXCfQ9QbIcN33GVbZNy3@xxxxxxxxxxxxxxxx wrote:
> Good day!
> I'm just a NB in Verilog design, sorry if my question is too stupid :)
> 
> I've started with free Xilinx ISE, but now i'm trying to do my best to
> take part in icarus verilog community.
> 
> I became familiar with IV modelling system, but synth restrain my activity
> - i get strange error with the simplest module:

Are you really intending to *synthesize* with Icarus Verilog? It
is most common in the Xilinx flow to use Icarus Verilog for simulation
then use xst for synthesis. If that is the case for you, then you
do not want to use the -tfpga flag to Icarus Verilog. That will
attempt to synthesize, when I think you want to only simulate.

Does this link help?
     <http://iverilog.wikia.com/wiki/User_Guide>

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."


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