Re: gEDA-user: VDD/VSS net confusion

["Brian Fuller" <brian@xxxxxxxxxx>]

I saw the question and made a real quick counter, but was hoping to modularize parts of it.
I was wondering how tough it would be to export simple parts of gscheme schematics into component files. Such as exporting a simple S-R latch to be able to easily create a D-FF to quickly work up to a binary counter.

Any suggestions?

On Mon, Jun 16, 2008 at 11:48 AM, John Luciani <jluciani@xxxxxxxxx> wrote:

On Mon, Jun 16, 2008 at 2:38 PM, Peter Clifton <pcjc2@xxxxxxxxx> wrote:

On Mon, 2008-06-16 at 13:34 -0400, John Luciani wrote:
> There are a number of places in your schematic where the active
> end of one symbol pin is placed on top of the active end of another.
> You need
> to move the symbols apart and connect the pins with nets.
>
> This should fix a number of your netlist problems.

Not true?

My mistake. I had thought that butting pins didn't connect.

Maybe I was thinking of a different EDA tool. With Orcad
I got into the habit of placing a net for all pin to pin connections.
I have always placed nets since.

(* jcl *)

--
http://www.luciani.org


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