Re: gEDA-user: putting it all together

[Ales Hvezda <ahvezda@seul.org>]

[ Ales here, I'm reposting this since majordomo didn't recognize the
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-- Cut here --
From: Jeff Storm <storm@chip-art.com>

Hi,

  Interesting ideas, but I think the problems are much more
 complicated. There is a releationship between cell size, or
 drive strength, and the distance the signal (wire) travels.

  Anything that makes the leap from "Icarus Verilog" to a
 "Magic .mag" needs to understand the impact of placement,
 distances, and wire lenghts to connect the different points
 each signal must hit... see -> Synopsys Physical Compiler

  A clock tree for a "flat" design might seem easy enough,
 but for a "hierarchal" designs (with  or modules)
 you need to keep track of the insertion delays for each
 branch of the clock tree... all the way down to the last
 flip-flop and memory component. This isn't too hard to keep
 track of, it's just easy to overlook it at first.

  I've had problems with clock trees that need to deliver
 a clock before the data to a "subsystems" (or module) that
 had it's own clock tree embedded in it. Even standard EDA
 tools don't have that case covered.

  FYI: I love Magic, limitations and all, used it and hacked
 at the code for aprox 10 years. Physical Designer - IC Layout
 designer by profession. I'm just learning about Icarus, and
 I'm a Sun/Solaris user type of software hack.

                       -J.Storm

cfk@pacbell.net wrote:
>
> It also seems that the placement issue can be modularized.
> A clock tree can be designed and placed seperately from
> various Verilog modules (or subsystems). It would seem that
> subsystems (or modules) would need to be placed in groups
> with their associated RatsNests displayed so that the members
> of the group can be re-arranged for appropriate signal placement.
> After the modules have been placed, then the routing can proceed.
> I know some of this borrows from PCB layout concepts, but I
> think it is basically a very similar problem