Re: gEDA-user: Icarus/NC mismatch -- who's right?

[Evan Lavelle <anti.spam1@xxxxxxxxxxxxx>]

Mark Schellhorn wrote:

> > Who's right? It kind of looks like the read_word() task fails to wait 
> > for @(ci) before leaving???

They're both right - you've got a race between your fill calculation and 
the inner read/display loop. for your code to work, the '@(ci)' timing 
control must lead immediately to a new fill level calculation, but 
there's no guarantee of this in Verilog. For Icarus, when the first 
@(ci) is hit, the drain process is rescheduled; for subsequent @(ci)'s, 
the fill level process is scheduled. This means that you go around the 
inner loop 5 times in Icarus (but presumably 4 times in NC-Verilog). 
After 5 iterations the FIFO has underflowed, so you carry on for ever 
(since regs are unsigned).

Evan