Re: gEDA-user: High speed decoupling (was: Simulation of ceramic capacitors, pairs and groups)

[sdb@xxxxxxxxxx (Stuart Brorson)]

> > >I have made a simulation to see how the capacitor pairs and groups actually
> > >behave:
> > >http://ronja.twibright.com/technotes/cercap.php
> > 
> > Thanks; very nice. However, I'm not sure that the numbers are right. The 
> > figure shows that a 10nF//100nF pair gives a low impedance (< ~1 Ohm) 
> > over a range of about 1.5MHz to 200MHz, which would make it ideal for 
> > decoupling high speed parts. I compared this with an old Cypress HOTLink 
> > app note where 22nF//100nF pairs were analysed, and the author's opinion 
> > was that this wasn't suitable for high-speed decoupling, because of a 
> > high resonant peak (~ 100 Ohm) at 150MHz. Your results show a peak of 
> > about 0.4 Ohm (at 30MHz), so are much better.
> > 
> > The differences are:
> > 
> > 1) The appnote assumes real parasitics of 5nH for a surface-mounted MLC 
> > cap, compared to your manufacturer's figures of 1.6 - 1.9nH. Your 
> > figures also seem to be for leaded caps: the SM figures are even lower.
> > 
> > 2) The appnote gives a lower ESR of about 30 mOhm, while you're using 
> > 100 - 150 mOhm. The peak height varies inversely with the ESR.
> > 
> > Anyone have any other thoughts on real in-system ESL and ESR numbers?
> 
> I think the ESR and ESL doesn't depend on if the capacitor is in system
> or alone. What we need is just a reliable source of numbers or someone
> measuring it. I don't know how I can measure ESR and ESL on a scope.

A couple of points:

*  I believe that ESR values can vary widely from mfr to mfr since the
details of the actual cap (i.e. structure, dielectric mix,
metalization, etc.) can vary.

*  Same for ESL.

*  Also, the ESL *does* depend upon how you drop the cap onto the
board.  If you have long pin escapes, vias, or narrow tracks, then the
impedance the rest of the circuit sees can vary.  The lesson here is
to use short, fat tracks and largish vias to pin escape to your
PWR/GND planes from your landing pads for minimum inductance. 

*  This sort of info is not easy to extract from app notes.  At this
level of detail, the folks who actually care about these properties
will do lab measurements of components on specially built test PCBs.
Measurements are done with S parameter analyzers over broad frequency
ranges, and then reduced to equivalent circuits for use in SPICE
simulation.

<flamebait advanced_apology="on">

*  Since your frequencies are more like dozens of MHz than tens of
GHz, why are you worrying so much about these minute levels of ESR and
ESL?  I'd hazard to guess that you can handily get by with ceramic
0.01uF 0805 caps on every device power pin, along with some tantalum
10uF bulk decoupling caps scattered around the board.

</flamebait>

Stuart