Mail Index
- Re: gEDA-user: gschem EPS output
- Re: gEDA-user: Howto draw copper at free areas?
- Re: gEDA-user: Howto draw copper at free areas?
- Re: gEDA-user: Prototyping with SMTs
- Re: gEDA-user: double side edge conector
- gEDA-user: Configuring layer colors and "route style" in PCB
- Re: gEDA-user: Configuring layer colors and "route style" in PCB
- Re: gEDA-user: Configuring layer colors and "route style" in PCB
- Re: gEDA-user: Configuring layer colors and "route style" in PCB
- Re: gEDA-user: Configuring layer colors and "route style" in PCB
- gEDA-user: pcb homepage vs. gedasymboles.org
- Re: gEDA-user: Outstanding improvement tasks
- Re: gEDA-user: gnucap has problems with text-named nodes?
- Re: gEDA-user: problem
- Re: gEDA-user: problem
- Re: gEDA-user: Dealing with really high-pin-count parts
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: A Suggestion FOR Karel
- gEDA-user: gEDA/gaf bug/feature/patch tracker
- Re: gEDA-user: gedasymbols.org update
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: Outstanding improvement tasks
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: Outstanding improvement tasks
- Re: gEDA-user: Outstanding improvement tasks
- Re: gEDA-user: local only mode for syms and footprints
- Re: gEDA-user: local only mode for syms and footprints
- Re: gEDA-user: gschem: locking fault
- Re: gEDA-user: Too many files
- Re: gEDA-user: footprint name's max length
- Re: gEDA-user: Rebuild of geda
- Re: gEDA-user: multi-part symbols [was: OGDI]
- Re: gEDA-user: footprint name's max length
- Re: gEDA-user: gschem -v
- Re: gEDA-user: gschem version symbol mismatch
- Re: gEDA-user: problem
- Re: gEDA-user: problem
- Re: gEDA-user: problem
- gEDA-user: adding buried vias for PCB
- gEDA-user: line thickness not shown in gerbv
- gEDA-user: several symbols and one footprint
- Re: gEDA-user: POLL: On politeness
- Re: gEDA-user: High speed decoupling (was: Simulation of ceramic capacitors, pairs and groups)
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: Configuring layer colors and "route style" in PCB
- Re: gEDA-user: Configuring layer colors and "route style" in PCB
- Re: gEDA-user: Configuring layer colors and "route style" in PCB
- Re: gEDA-user: Configuring layer colors and "route style" in PCB
- Re: gEDA-user: Style of rats nest lines
- Re: gEDA-user: routing questions
- Re: gEDA-user: routing questions
- Re: gEDA-user: routing questions
- Re: gEDA-user: footprint name's max length
- Re: gEDA-user: PCB HID status
- Re: gEDA-user: PCB HID status
- Re: gEDA-user: Can't load layouts created with current pcb,
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: gtk hid bug
- Re: gEDA-user: pcb optimize rats nest error
- Re: gEDA-user: revert in pcb_hid
- Re: gEDA-user: window focus vs. gtk_HID
- Re: gEDA-user: OT: lead-free question
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: PCB: Stale rat's nest?
- From: Carlos Nieves Ónega
- Re: gEDA-user: gschem text overbars
- From: Carlos Nieves Ónega
- Re: gEDA-user: Double refdes
- From: Carlos Nieves Ónega
- Re: gEDA-user: Double refdes
- From: Carlos Nieves Ónega
- Re: gEDA-user: pintype of hidden power-pins
- From: Carlos Nieves Ónega
- Re: gEDA-user: Double refdes
- From: Carlos Nieves Ónega
- Re: gEDA-user: Too many files
- From: Carlos Nieves Ónega
- Re: gEDA-user: Fwd: [Open-graphics] How to get more eyes on OGD1 schematic?
- From: Carlos Nieves Ónega
- gEDA-user: multi-part symbols [was: OGDI]
- From: Carlos Nieves Ónega
- Re: gEDA-user: multi-part symbols [was: OGDI]
- From: Carlos Nieves Ónega
- Re: gEDA-user: Adding symbol version mismatch
- From: Carlos Nieves Ónega
- Re: gEDA-user: gschem -v
- From: Carlos Nieves Ónega
- Re: gEDA-user: pcb footprint creation: Soldermask clearance
- From: Carlos Nieves Ónega
- gEDA-user: Text outside of PCB area?
- gEDA-user: PCB text/symbol sizes
- Re: gEDA-user: PCB text/symbol sizes
- Re: gEDA-user: Olimex and PCB?
- gEDA-user: Din connector footprints and symbols
- Re: gEDA-user: Obsolete Pin syntax in pcb-cvs.pdf
- gEDA-user: IPC-D-356 usage?
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: Edge ringing filtering
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB DRC IPC-A600D
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: pcb footprint syntax
- Re: gEDA-user: Howto update footprint in pcb?
- Re: gEDA-user: pcb footprint syntax
- Re: gEDA-user: Howto update footprint in pcb?
- Re: gEDA-user: Howto update footprint in pcb?
- gEDA-user: lesstif vs gtk (no flame please)
- Re: gEDA-user: A Suggestion FOR Karel
- Re: gEDA-user: footprints
- Re: gEDA-user: DB9 -> DE9
- Re: gEDA-user: problem
- Re: gEDA-user: problem
- Re: gEDA-user: PCB 'surface mount' pad autoroute error
- Re: gEDA-user: PCB 'surface mount' pad autoroute error
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: Another autorouter bug
- Re: gEDA-user: Soldering fine pitch chips
- Re: gEDA-user: pcb file syntax docs
- Re: gEDA-user: New project release
- Re: gEDA-user: New project release
- Re: gEDA-user: New project release
- gEDA-user: footprint= values
- Re: gEDA-user: Looking for footprint of 1808
- Re: gEDA-user: Fwd: [Open-graphics] How to get more eyes on OGD1 schematic?
- gEDA-user: PCB footprints on gedasymbols.org
- Re: gEDA-user: footprint name's max length
- Re: gEDA-user: footprint name's max length
- Re: gEDA-user: CVS PCB
- Re: gEDA-user: CVS PCB
- Re: gEDA-user: PCB footprints quick reference added to wiki.
- Re: gEDA-user: pcb HID has been merged!
- gEDA-user: pcb-20060321 snapshot available
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: gerbv even more broken than pcb in non-"C"-locale.
- Re: gEDA-user: Changing width of lines in pcb
- Re: gEDA-user: Drill helpers generated by pcb
- Re: gEDA-user: pcb footprint creation: Soldermask clearance
- Re: gEDA-user: footprint creation war
- Re: gEDA-user: Drill helpers generated by pcb
- Re: gEDA-user: Drill helpers generated by pcb
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: ALPS 6mm tactile footprint
- Re: gEDA-user: pcb HID has been merged!
- gEDA-user: pcb documentation build patches
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: gtk hid bug
- Re: gEDA-user: gtk hid bug
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: bug - GTK PCB disable net doesn't work
- gEDA-user: anyone use pcb save connection data?
- Re: gEDA-user: gedasymbols.org update
- Re: gEDA-user: gedasymbols.org update
- Re: gEDA-user: pcb file syntax docs
- Re: gEDA-user: Changing soldermask in PCB
- Re: gEDA-user: gedasymbols.org update
- Re: gEDA-user: gedasymbols.org update
- Re: gEDA-user: Which symbol is used?
- Re: gEDA-user: gedasymbols.org update
- Re: gEDA-user: Text outside of PCB area?
- Re: gEDA-user: max board size in pcb
- Re: gEDA-user: max board size in pcb
- gEDA-user: OT: lead-free question
- Re: gEDA-user: Too many files
- Re: gEDA-user: challenge from sci.electronics.cad
- Re: gEDA-user: lesstif vs gtk (no flame please)
- gEDA-user: tactile switch footprint
- gEDA-user: ALPS 6mm tactile footprint
- Re: gEDA-user: ALPS 6mm tactile footprint
- Re: gEDA-user: local only mode for syms and footprints
- gEDA-user: gschem's "Save All" doesn't save all
- Re: gEDA-user: High speed decoupling (was: Simulation of ceramic capacitors, pairs and groups)
- Re: gEDA-user: High speed decoupling
- Re: gEDA-user: Rebuild of geda
- gEDA-user: gschem -v
- gEDA-user: gschem -v
- gEDA-user: pcb optimize rats nest error
- Re: gEDA-user: pcb optimize rats nest error
- Re: gEDA-user: pcb, optimize rats nest with polygon
- Re: gEDA-user: pcb, optimize rats nest with polygon
- Re: gEDA-user: pcb, optimize rats nest with polygon
- gEDA-user: PCB - dragging tracks at 45 degrees
- Re: gEDA-user: Soldering fine pitch chips
- Re: gEDA-user: Obsolete Pin syntax in pcb-cvs.pdf
- Re: gEDA-user: Postscript PCB lines
- Re: gEDA-user: Postscript PCB lines
- Re: gEDA-user: local only mode for syms and footprints
- Re: gEDA-user: Postscript PCB lines
- Re: gEDA-user: Postscript PCB lines
- gEDA-user: max board size in pcb
- Re: gEDA-user: max board size in pcb
- Re: gEDA-user: Postscript PCB lines
- Re: gEDA-user: Wiki entries while doing my first project with pcb
- Re: gEDA-user: max board size in pcb
- Re: gEDA-user: searching in pcb
- Re: gEDA-user: Dealing with really high-pin-count parts
- Re: gEDA-user: Postscript PCB lines
- gEDA-user: The PCB Postscript bug
- Re: gEDA-user: Dealing with really high-pin-count parts
- Re: gEDA-user: Dealing with really high-pin-count parts
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: Changing soldermask in PCB
- Re: gEDA-user: PCB minimum plated hole
- Re: gEDA-user: PCB DRC text denting
- Re: gEDA-user: HOLES & vias
- Re: gEDA-user: HOLES & vias
- Re: gEDA-user: PCB minimum plated hole
- Re: gEDA-user: Select in PCB sometimes doesn't work
- Re: gEDA-user: pcb footprint syntax
- gEDA-user: gedasymbols.org update
- Re: gEDA-user: HOLES & vias
- Re: gEDA-user: gedasymbols.org update
- Re: gEDA-user: Embedded Power Pins
- Re: gEDA-user: Changing soldermask in PCB
- Re: gEDA-user: PCB minimum plated hole
- Re: gEDA-user: HOLES & vias
- Re: gEDA-user: gedasymbols.org update
- Re: gEDA-user: PCB TRACKS
- Re: gEDA-user: pink colour in PCB
- Re: gEDA-user: footprints
- Re: gEDA-user: footprints
- Re: gEDA-user: DB9 -> DE9
- Re: gEDA-user: gedasymbols.org update
- Re: gEDA-user: gedasymbols.org update
- Re: gEDA-user: gedasymbols.org update
- Re: gEDA-user: Dealing with really high-pin-count parts
- Re: gEDA-user: footprints
- Re: gEDA-user: Text outside of PCB area?
- Re: gEDA-user: Text outside of PCB area?
- Re: gEDA-user: PCB 'surface mount' pad autoroute error
- Re: gEDA-user: line thickness not shown in gerbv
- Re: gEDA-user: rats nest
- Re: gEDA-user: Style of rats nest lines
- Re: gEDA-user: Layers limit in pcb
- Re: gEDA-user: gschem EPS output
- Re: gEDA-user: routing questions
- Re: gEDA-user: Reverting in PCB
- Re: gEDA-user: gschem EPS output
- gEDA-user: more gedasymbols stuff
- Re: gEDA-user: Another autorouter bug
- Re: gEDA-user: more gedasymbols stuff
- Re: gEDA-user: routing questions
- Re: gEDA-user: routing questions
- Re: gEDA-user: Autorouter issues...
- Re: gEDA-user: Autorouter issues...
- Re: gEDA-user: PCB on gEDA CDROM
- Re: gEDA-user: more gedasymbols stuff
- Re: gEDA-user: more gedasymbols stuff
- Re: gEDA-user: Howto draw copper at free areas?
- Re: gEDA-user: Howto draw copper at free areas?
- Re: gEDA-user: component values on silk layer?
- Re: gEDA-user: Howto draw copper at free areas?
- Re: gEDA-user: component values on silk layer?
- Re: gEDA-user: Howto draw copper at free areas?
- gEDA-user: pcb file syntax docs
- Re: gEDA-user: PCB on gEDA CDROM
- Re: gEDA-user: New project release
- Re: gEDA-user: "Open Pinout Menu" issue?
- Re: gEDA-user: double side edge conector
- Re: gEDA-user: PCB text/symbol sizes
- Re: gEDA-user: CVS PCB
- gEDA-user: challenge from sci.electronics.cad
- Re: gEDA-user: challenge from sci.electronics.cad
- gEDA-user: CSV files on gedasymbols.org
- Re: gEDA-user: Gedasymbols footprints
- gEDA-user: PCB HID status
- Re: gEDA-user: challenge from sci.electronics.cad
- Re: gEDA-user: Olimex and PCB?
- Re: gEDA-user: Refdes odd issue
- Re: gEDA-user: Can't load layouts created with current pcb,
- Re: gEDA-user: Can't load layouts created with current pcb,
- Re: gEDA-user: Can't load layouts created with current pcb,
- Re: gEDA-user: Can't load layouts created with current pcb,
- Re: gEDA-user: Can't load layouts created with current pcb,
- Re: gEDA-user: Refdes odd issue
- Re: gEDA-user: Can't load layouts created with current pcb,
- Re: gEDA-user: Can't load layouts created with current pcb,
- Re: gEDA-user: Can't load layouts created with current pcb,
- Re: gEDA-user: tragesym and multiple slots
- Re: gEDA-user: tragesym and multiple slots
- Re: gEDA-user: tragesym and multiple slots
- gEDA-user: pcb HID has been merged!
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: Drill helpers generated by pcb
- Re: gEDA-user: pcb footprint creation: Soldermask clearance
- Re: gEDA-user: footprint creation war
- Re: gEDA-user: Drill helpers generated by pcb
- Re: gEDA-user: Drill helpers generated by pcb
- Re: gEDA-user: Drill helpers generated by pcb
- Re: gEDA-user: Drill helpers generated by pcb
- gEDA-user: hid dependencies build bug fixed
- gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: Disable nets in GTK PCB doesn't survive
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: Disable nets in GTK PCB doesn't survive
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: revert in pcb_hid
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: revert in pcb_hid
- Re: gEDA-user: hidename ?
- gEDA-user: FYI: new ethernet chip
- Re: gEDA-user: FYI: new ethernet chip
- Re: gEDA-user: FYI: new ethernet chip
- Re: gEDA-user: FYI: new ethernet chip
- Re: gEDA-user: Bad highlighting
- Re: gEDA-user: pcb, optimize rats nest with polygon
- Re: gEDA-user: pcb, optimize rats nest with polygon
- Re: gEDA-user: F problem
- Re: gEDA-user: Fwd: [Open-graphics] How to get more eyes on OGD1 schematic?
- gEDA-user: hierarchical gschem examples?
- gEDA-user: High speed decoupling (was: Simulation of ceramic capacitors, pairs and groups)
- Re: gEDA-user: High speed decoupling
- Re: gEDA-user: challenge from sci.electronics.cad
- Re: gEDA-user: Embedded Power Pins
- Re: gEDA-user: an unplated via - a capacitor inside a board
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: Postscript PCB lines
- From: George M. Gallant, Jr.
- Re: gEDA-user: max board size in pcb
- From: George M. Gallant, Jr.
- gEDA-user: Rebuild of geda
- From: George M. Gallant, Jr.
- Re: gEDA-user: Rebuild of geda
- From: George M. Gallant, Jr.
- Re: gEDA-user: Rebuild of geda
- From: George M. Gallant, Jr.
- Re: gEDA-user: Rebuild of geda
- From: George M. Gallant, Jr.
- gEDA-user: Adding symbol version mismatch
- From: George M. Gallant, Jr.
- gEDA-user: help with linux install please
- Re: gEDA-user: help with linux install please
- gEDA-user: PCB HID LibGD compile problem
- Re: gEDA-user: rats nest
- Re: gEDA-user: PCB 'surface mount' pad autoroute error
- Re: gEDA-user: Another autorouter bug
- Re: gEDA-user: PCB 'surface mount' pad autoroute error
- Re: gEDA-user: Autorouter issues...
- Re: gEDA-user: Howto draw copper at free areas?
- Re: gEDA-user: Autorouter segfaults
- Re: gEDA-user: PCB - dragging tracks at 45 degrees
- Re: gEDA-user: PCB copper areas too close
- Re: gEDA-user: Bug in PCB DRC
- gEDA-user: ïschem lock and unlock
- Re: gEDA-user: ïschem lock and unlock
- Re: gEDA-user: Re: gEDA-user: gschem lock and unlock
- gEDA-user: double side edge conector
- Re: gEDA-user: double side edge conector
- gEDA-user: Looking for footprint of 1808
- Re: gEDA-user: Looking for footprint of 1808
- gEDA-user: cat: write error: Broke pipe
- gEDA-user: footprint name's max length
- Re: gEDA-user: footprint name's max length
- Re: gEDA-user: footprint name's max length
- Re: gEDA-user: footprint name's max length
- Re: gEDA-user: footprint name's max length
- gEDA-user: Ssolving M4 lib nightmare
- gEDA-user: Footprint file comment line ?
- Re: gEDA-user: Footprint file comment line ?
- gEDA-user: pcb reference number font size
- Re: gEDA-user: pcb reference number font size
- gEDA-user: hidename ?
- Re: gEDA-user: hidename ?
- gEDA-user:
- gEDA-user: Tiling of PCB generated gerber files
- Re: gEDA-user: FYI: new ethernet chip
- gEDA-user: pc104 designs?
- [no subject]
- Re: gEDA-user: component values on silk layer?
- From: Jean-Francois Blavier
- Re: gEDA-user: IPC-D-356 usage?
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: Edge ringing filtering
- Re: gEDA-user: Edge ringing filtering
- Re: gEDA-user: Text outside of PCB area?
- Re: gEDA-user: The PCB Postscript bug
- Re: gEDA-user: Embedded Power Pins
- Re: gEDA-user: Edge ringing filtering
- Re: gEDA-user: gedasymbols.org update
- Re: gEDA-user: Edge ringing filtering
- Re: gEDA-user: High speed decoupling (was: Simulation of ceramic capacitors, pairs and groups)
- Re: gEDA-user: gschem's "Save All" doesn't save all
- Re: gEDA-user: High speed decoupling (was: Simulation of ceramic capacitors, pairs and groups)
- Re: gEDA-user: High speed decoupling
- Re: gEDA-user: High speed decoupling
- gEDA-user: Symbols as graphical docs
- Re: gEDA-user: multi-part symbols [was: OGDI]
- Re: gEDA-user: tragesym and multiple slots
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: PCB: Stale rat's nest?
- gEDA-user: recommendation about logic analyzers
- Re: gEDA-user: local oly mode for syms and footprints
- Re: gEDA-user: local only mode for syms and footprints
- Re: gEDA-user: HOLES & vias
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB: Stale rat's nest?
- gEDA-user: Embedded Power Pins
- Re: gEDA-user: RJ45
- Re: gEDA-user: Embedded Power Pins
- Re: gEDA-user: Embedded Power Pins
- gEDA-user: Re: gEDA-user: gschem lock and unlock
- Re: gEDA-user: local only mode for syms and footprints
- Re: gEDA-user: PCB Libraries
- Re: gEDA-user: Tiling of PCB generated gerber files
- Re: gEDA-user: footprint name's max length
- Re: gEDA-user: Footprint file comment line ?
- Re: gEDA-user: PCB pin and pad _flags_ reference help.
- Re: gEDA-user: hierarchical gschem examples?
- Re: gEDA-user: Changing width of lines in pcb
- Re: gEDA-user: tactile switch footprint
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: ALPS 6mm tactile footprint
- Re: gEDA-user: pcb reference number font size
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: FYI: new ethernet chip
- Re: gEDA-user: PCB colour spread
- Re: gEDA-user: max board size in pcb
- Re: gEDA-user: High speed decoupling
- Re: gEDA-user: an unplated via - a capacitor inside a board
- Re: gEDA-user: Fwd: [Open-graphics] How to get more eyes on OGD1 schematic?
- Re: gEDA-user: Fwd: [Open-graphics] How to get more eyes on OGD1 schematic?
- Re: gEDA-user: Fwd: [Open-graphics] How to get more eyes on OGD1 schematic?
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- gEDA-user: Obsolete information in pcb-cvs.pdf
- gEDA-user: Obsolete Pin syntax in pcb-cvs.pdf
- gEDA-user: Suggestion for PCB manual
- gEDA-user: Edge ringing filtering
- gEDA-user: PCB double viadrillinghole
- gEDA-user: Changing soldermask in PCB
- gEDA-user: Minimum soldermask for PCB
- gEDA-user: PCB minimum plated hole
- gEDA-user: PCB DRC IPC-A600D
- gEDA-user: PCB DRC text denting
- Re: gEDA-user: Rotating selection in PCB
- Re: gEDA-user: DB9 -> DE9
- Re: gEDA-user: Rotating selection in PCB
- Re: gEDA-user: footprints
- Re: gEDA-user: Select in PCB sometimes doesn't work
- Re: gEDA-user: pink colour in PCB
- gEDA-user: PCB board size limitation
- gEDA-user: Patch for PCB fab file author
- Re: gEDA-user: max board size in pcb
- Re: gEDA-user: Obsolete Pin syntax in pcb-cvs.pdf
- Re: gEDA-user: problem
- Re: gEDA-user: HOLES & vias
- Re: gEDA-user: Changing soldermask in PCB
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB minimum plated hole
- Re: gEDA-user: HOLES & vias
- Re: gEDA-user: Changing soldermask in PCB
- Re: gEDA-user: gedasymbols.org update
- Re: gEDA-user: PCB TRACKS
- Re: gEDA-user: PCB TRACKS
- Re: gEDA-user: Edge ringing filtering
- Re: gEDA-user: pink colour in PCB
- Re: gEDA-user: A Suggestion FOR Karel
- Re: gEDA-user: footprints
- Re: gEDA-user: footprints
- gEDA-user: Double refdes
- Re: gEDA-user: OT: lead-free question
- Re: gEDA-user: Edge ringing filtering
- Re: gEDA-user: footprints
- Re: gEDA-user: A Suggestion FOR Karel
- Re: gEDA-user: HOLES & vias
- Re: gEDA-user: help with linux install please
- Re: gEDA-user: Embedded Power Pins
- Re: gEDA-user: help with linux install please
- Re: gEDA-user: gedasymbols.org update
- gEDA-user: gecos patch
- Re: gEDA-user: help with linux install please
- gEDA-user: netname for nets as default
- gEDA-user: gnucap has problems with text-named nodes?
- gEDA-user: SWF tutorials
- gEDA-user: Simulation of ceramic capacitors, pairs and groups
- gEDA-user: Soldering fine pitch chips
- Re: gEDA-user: High speed decoupling (was: Simulation of ceramic capacitors, pairs and groups)
- gEDA-user: PCB on gEDA CDROM
- Re: gEDA-user: Layers limit in pcb
- Re: gEDA-user: more gedasymbols stuff
- Re: gEDA-user: more gedasymbols stuff
- gEDA-user: an unplated via - a capacitor inside a board
- gEDA-user: gEDA save as dialog
- gEDA-user: Too many files
- gEDA-user: Fixed version of SMD footprint creation guideline
- Re: gEDA-user: an unplated via - a capacitor inside a board
- Re: gEDA-user: component values on silk layer?
- Re: gEDA-user: Howto draw copper at free areas?
- Re: gEDA-user: Prototyping with SMTs
- Re: gEDA-user: Soldering fine pitch chips
- Re: gEDA-user: PCB on gEDA CDROM
- Re: gEDA-user: Autorouter segfaults
- gEDA-user: gschem: locking fault
- Re: gEDA-user: Too many files
- Re: gEDA-user: High speed decoupling
- Re: gEDA-user: Autorouter segfaults
- Re: gEDA-user: New project release
- Re: gEDA-user: Autorouter segfaults
- Re: gEDA-user: "Open Pinout Menu" issue?
- Re: gEDA-user: Too many files
- Re: gEDA-user: Looking for footprint of 1808
- gEDA-user: gschem hide text cancel
- gEDA-user: CVS PCB
- gEDA-user: Symbol version mismatch
- gEDA-user: Gedasymbols footprints
- Re: gEDA-user: Olimex and PCB?
- Re: gEDA-user: challenge from sci.electronics.cad
- Re: gEDA-user: Can't load layouts created with current pcb,
- Re: gEDA-user: Can't load layouts created with current pcb,
- Re: gEDA-user: pcb-20060321 snapshot available
- gEDA-user: PCB command window fails
- gEDA-user: PCB command window failure
- Re: gEDA-user: footprint creation war
- Re: gEDA-user: pcb footprint creation: Soldermask clearance
- Re: gEDA-user: tactile switch footprint
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: ALPS 6mm tactile footprint
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- gEDA-user: PCB action proc 'setthermal' not found.
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: pcb footprint creation: Soldermask clearance
- gEDA-user: bug - GTK PCB disable net doesn't work
- gEDA-user: Disable nets in GTK PCB doesn't survive
- gEDA-user: PCB changeclearsize(selectedpads) doesn't work
- gEDA-user: gschem version symbol mismatch
- Re: gEDA-user: Disable nets in GTK PCB doesn't survive
- Re: gEDA-user: basic anti-EMI design q
- gEDA-user: Continuing drawing a line
- gEDA-user: GTK PCB crashes with losing the data
- Re: gEDA-user: GTK PCB crashes with losing the data
- gEDA-user: PCB colour spread
- gEDA-user: Bad highlighting
- Re: gEDA-user: pcb, optimize rats nest with polygon
- gEDA-user: F problem
- gEDA-user: PCB copper areas too close
- gEDA-user: Bug in PCB DRC
- gEDA-user: PCB is duplicating polygons
- gEDA-user: local oly mode for syms and footprints
- Re: gEDA-user: local only mode for syms and footprints
- Re: gEDA-user: local only mode for syms and footprints
- gEDA-user: Wiki entries while doing my first project with pcb
- gEDA-user: searching in pcb
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: A Suggestion FOR Karel
- Re: gEDA-user: Outstanding improvement tasks
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB: Stale rat's nest?
- gEDA-user: pcb footprint syntax
- gEDA-user: some gattrib suggestions
- gEDA-user: Howto update footprint in pcb?
- Re: gEDA-user: some gattrib suggestions
- Re: gEDA-user: pcb footprint syntax
- Re: gEDA-user: Howto update footprint in pcb?
- Re: gEDA-user: Howto update footprint in pcb?
- Re: gEDA-user: gEDA/gaf bug/feature/patch tracker
- Re: gEDA-user: Embedded Power Pins
- Re: gEDA-user: Embedded Power Pins
- gEDA-user: Which symbol is used?
- Re: gEDA-user: Which symbol is used?
- Re: gEDA-user: Double refdes
- gEDA-user: Style of rats nest lines
- Re: gEDA-user: rats nest
- Re: gEDA-user: gschem EPS output
- Re: gEDA-user: gschem EPS output
- gEDA-user: Autorouter segfaults
- gEDA-user: routing questions
- Re: gEDA-user: more gedasymbols stuff
- Re: gEDA-user: routing questions
- Re: gEDA-user: routing questions
- Re: gEDA-user: Double refdes
- Re: gEDA-user: routing questions
- Re: gEDA-user: Double refdes
- Re: gEDA-user: routing questions
- gEDA-user: Howto draw copper at free areas?
- Re: gEDA-user: Howto draw copper at free areas?
- Re: gEDA-user: Howto draw copper at free areas?
- gEDA-user: component values on silk layer?
- Re: gEDA-user: Howto draw copper at free areas?
- Re: gEDA-user: component values on silk layer?
- Re: gEDA-user: component values on silk layer?
- Re: gEDA-user: High speed decoupling
- Re: gEDA-user: Too many files
- Re: gEDA-user: Autorouter segfaults
- Re: gEDA-user: New project release
- Re: gEDA-user: Autorouter segfaults
- Re: gEDA-user: Autorouter segfaults
- Re: gEDA-user: Fwd: [Open-graphics] How to get more eyes on OGD1 schematic?
- Re: gEDA-user: several symbols and one footprint
- Re: gEDA-user: Changing width of lines in pcb
- Re: gEDA-user: Changing width of lines in pcb
- Re: gEDA-user: Changing width of lines in pcb
- Re: gEDA-user: Changing width of lines in pcb
- Re: gEDA-user: pcb footprint creation: Soldermask clearance
- Re: gEDA-user: pcb footprint creation: Soldermask clearance
- Re: gEDA-user: PCB colour spread
- Re: gEDA-user: PCB question
- Re: gEDA-user: pcb, optimize rats nest with polygon
- Re: gEDA-user: pcb, optimize rats nest with polygon
- Re: gEDA-user: pcb, optimize rats nest with polygon
- gEDA-user: pcb, optimize rats nest with polygon
- Re: gEDA-user: pcb, optimize rats nest with polygon
- Re: gEDA-user: help with linux install please
- Re: gEDA-user: Embedded Power Pins
- Re: gEDA-user: routing questions
- Re: gEDA-user: an unplated via - a capacitor inside a board
- Re: gEDA-user: New project release
- Re: gEDA-user: challenge from sci.electronics.cad
- gEDA-user: PCB Route style
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: gedasymbols.org update
- gEDA-user: RJ45
- gEDA-user: RJ45
- gEDA-user: gschem EPS output
- Re: gEDA-user: gschem EPS output
- gEDA-user: Reverting in PCB
- Re: gEDA-user: gschem EPS output
- Re: gEDA-user: Reverting in PCB
- Re: gEDA-user: New project release
- Re: gEDA-user: Too many files
- Re: gEDA-user: PCB HID status
- Re: gEDA-user: PCB HID status
- gEDA-user: gtk hid bug
- Re: gEDA-user: gtk hid bug
- gEDA-user: revert in pcb_hid
- Re: gEDA-user: gtk hid bug
- Re: gEDA-user: revert in pcb_hid
- Re: gEDA-user: gtk hid bug
- gEDA-user: pcb_HID vs. soldermask
- Re: gEDA-user: Bad highlighting
- Re: gEDA-user: F problem
- gEDA-user: window focus vs. gtk_HID
- Re: gEDA-user: Edge ringing filtering
- gEDA-user: HOLES & vias
- Re: gEDA-user: HOLES & vias
- Re: gEDA-user: help with linux install please
- gEDA-user: rats nest
- gEDA-user: PCB Libraries
- Re: gEDA-user: PCB Libraries
- Re: gEDA-user: Dealing with really high-pin-count parts
- Re: gEDA-user: recommendation about logic analyzers
- Re: gEDA-user: OT: lead-free question
- Re: gEDA-user: OT: lead-free question
- Re: gEDA-user: Prototyping with SMTs
- Re: gEDA-user: challenge from sci.electronics.cad
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: FYI: new ethernet chip
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: local only mode for syms and footprints
- Re: gEDA-user: problem
- Re: gEDA-user: gschem EPS output
- Re: gEDA-user: gschem EPS output
- gEDA-user: Dealing with really high-pin-count parts
- gEDA-user: Outstanding improvement tasks
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: Outstanding improvement tasks
- Re: gEDA-user: Outstanding improvement tasks
- Re: gEDA-user: gecos patch
- Re: gEDA-user: Outstanding improvement tasks
- gEDA-user: Layers limit in pcb
- Re: gEDA-user: gschem EPS output
- Re: gEDA-user: local only mode for syms and footprints
- gEDA-user: Fwd: [Open-graphics] How to get more eyes on OGD1 schematic?
- Re: gEDA-user: footprints
- Re: gEDA-user: High speed decoupling (was: Simulation of ceramic capacitors, pairs and groups)
- Re: gEDA-user: Prototyping with SMTs
- Re: gEDA-user: Howto draw copper at free areas?
- Re: gEDA-user: High speed decoupling
- Re: gEDA-user: challenge from sci.electronics.cad
- Re: gEDA-user: challenge from sci.electronics.cad
- gEDA-user: PCB footprints quick reference added to wiki.
- gEDA-user: PCB pin and pad _flags_ reference help.
- Re: gEDA-user: PCB footprints quick reference added to wiki.
- Re: gEDA-user: Drill helpers generated by pcb
- gEDA-user: footprint creation war
- Re: gEDA-user: footprint creation war
- Re: gEDA-user: footprint creation war
- Re: gEDA-user: Drill helpers generated by pcb
- Re: gEDA-user: Drill helpers generated by pcb
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: pcb footprint creation: Soldermask clearance
- Re: gEDA-user: pcb footprint creation: Soldermask clearance
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: Olimex and PCB?
- From: Philipp Klaus Krause
- gEDA-user: Can't load layouts created with current pcb,
- From: Philipp Klaus Krause
- Re: gEDA-user: Can't load layouts created with current pcb,
- From: Philipp Klaus Krause
- Re: gEDA-user: Can't load layouts created with current pcb,
- From: Philipp Klaus Krause
- Re: gEDA-user: Can't load layouts created with current pcb,
- From: Philipp Klaus Krause
- Re: gEDA-user: Can't load layouts created with current pcb,
- From: Philipp Klaus Krause
- Re: gEDA-user: Can't load layouts created with current pcb,
- From: Philipp Klaus Krause
- Re: gEDA-user: Can't load layouts created with current pcb,
- From: Philipp Klaus Krause
- Re: gEDA-user: Can't load layouts created with current pcb,
- From: Philipp Klaus Krause
- Re: gEDA-user: Can't load layouts created with current pcb,
- From: Philipp Klaus Krause
- gEDA-user: gerbv even more broken than pcb in non-"C"-locale.
- From: Philipp Klaus Krause
- gEDA-user: pcb footprint creation: Soldermask clearance
- From: Philipp Klaus Krause
- Re: gEDA-user: Olimex and PCB?
- From: Philipp Klaus Krause
- gEDA-user: Changing width of lines in pcb
- From: Philipp Klaus Krause
- Re: gEDA-user: Changing width of lines in pcb
- From: Philipp Klaus Krause
- gEDA-user: Drill helpers generated by pcb
- From: Philipp Klaus Krause
- Re: gEDA-user: Drill helpers generated by pcb
- From: Philipp Klaus Krause
- Re: gEDA-user: pcb footprint creation: Soldermask clearance
- From: Philipp Klaus Krause
- Re: gEDA-user: pcb footprint creation: Soldermask clearance
- From: Philipp Klaus Krause
- Re: gEDA-user: footprint creation war
- From: Philipp Klaus Krause
- Re: gEDA-user: Drill helpers generated by pcb
- From: Philipp Klaus Krause
- Re: gEDA-user: Drill helpers generated by pcb
- From: Philipp Klaus Krause
- Re: gEDA-user: Soldering fine pitch chips
- Re: gEDA-user: challenge from sci.electronics.cad
- Re: gEDA-user: footprint creation war
- Re: gEDA-user: footprint creation war
- Re: gEDA-user: footprint creation wary
- Re: gEDA-user: pcb optimize rats nest error
- Re: gEDA-user: pcb optimize rats nest error
- Re: gEDA-user: pcb optimize rats nest error
- Re: gEDA-user: New project release
- Re: gEDA-user: gedasymbols.org update
- gEDA-user: Prototyping with SMTs
- Re: gEDA-user: tragesym and multiple slots
- gEDA-user: PCB question
- Re: gEDA-user: OT: lead-free question
- Re: gEDA-user: OT: lead-free question
- Re: gEDA-user: Tiling of PCB generated gerber files
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: ALPS 6mm tactile footprint
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: ALPS 6mm tactile footprint
- Re: gEDA-user: problem
- Re: gEDA-user: problem
- Re: gEDA-user: problem
- Re: gEDA-user: local only mode for syms and footprints
- Re: gEDA-user: Wiki entries while doing my first project with pcb
- Re: gEDA-user: Outstanding improvement tasks
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB minimum plated hole
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: Embedded Power Pins
- Re: gEDA-user: Embedded Power Pins
- Re: gEDA-user: PCB minimum plated hole
- Re: gEDA-user: problem
- Re: gEDA-user: OT: lead-free question
- Re: gEDA-user: OT: lead-free question
- Re: gEDA-user: Double refdes
- Re: gEDA-user: Double refdes
- Re: gEDA-user: High speed decoupling (was: Simulation of ceramic capacitors, pairs and groups)
- Re: gEDA-user: PCB on gEDA CDROM
- Re: gEDA-user: Rebuild of geda
- Re: gEDA-user: Fwd: [Open-graphics] How to get more eyes on OGD1 schematic?
- Re: gEDA-user: PCB footprints quick reference added to wiki.
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: Drill helpers generated by pcb
- Re: gEDA-user: pcb footprint creation: Soldermask clearance
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: basic anti-EMI design q
- Re: gEDA-user: pcb footprint creation: Soldermask clearance
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: pcb HID has been merged!
- Re: gEDA-user: GTK PCB crashes with losing the data
- Re: gEDA-user: GTK PCB crashes with losing the data
- gEDA-user: Robotics competition at Trinity College, Hartford CT, USA
- Re: gEDA-user: Outstanding improvement tasks
- Re: gEDA-user: challenge from sci.electronics.cad
- gEDA-user: tragesym and multiple slots
- Re: gEDA-user: tragesym and multiple slots
- Re: gEDA-user: tragesym and multiple slots
- Re: gEDA-user: tragesym and multiple slots
- gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: HOLES & vias
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: PCB: Stale rat's nest?
- Re: gEDA-user: gedasymbols.org update
- Re: gEDA-user: Embedded Power Pins
- gEDA-user: PCB 'surface mount' pad autoroute error
- Re: gEDA-user: PCB 'surface mount' pad autoroute error
- Re: gEDA-user: PCB 'surface mount' pad autoroute error
- Re: gEDA-user: PCB 'surface mount' pad autoroute error
- Re: gEDA-user: PCB 'surface mount' pad autoroute error
- gEDA-user: Another autorouter bug
- Re: gEDA-user: PCB 'surface mount' pad autoroute error
- gEDA-user: Autorouter issues...
- Re: gEDA-user: Autorouter issues...
- Re: gEDA-user: Howto draw copper at free areas?
- gEDA-user: New project release
- Re: gEDA-user: New project release
- Re: gEDA-user: New project release
- Re: gEDA-user: New project release
- Re: gEDA-user: New project release
- gEDA-user: "Open Pinout Menu" issue?
- Re: gEDA-user: "Open Pinout Menu" issue?
- gEDA-user: Refdes odd issue
- Re: gEDA-user: Refdes odd issue
- Re: gEDA-user: Refdes odd issue
- Re: gEDA-user: footprint creation war
- gEDA-user: announce: new version (0.6.7) of the ngspice frontend easy_spice
- Re: gEDA-user: Embedded Power Pins
- Re: gEDA-user: Double refdes
- Re: gEDA-user: Postscript PCB lines
- Re: gEDA-user: Postscript PCB lines
- Re: gEDA-user: Postscript PCB lines
- Re: gEDA-user: Postscript PCB lines
- Re: gEDA-user: Postscript PCB lines
- Re: gEDA-user: Dealing with really high-pin-count parts
- Re: gEDA-user: Embedded Power Pins
- Re: gEDA-user: HOLES & vias
- Re: gEDA-user: Embedded Power Pins
- Re: gEDA-user: Soldering fine pitch chips
- Re: gEDA-user: an unplated via - a capacitor inside a board
- Re: gEDA-user: Too many files
- Re: gEDA-user: Fwd: [Open-graphics] How to get more eyes on OGD1 schematic?
- Re: gEDA-user: Fwd: [Open-graphics] How to get more eyes on OGD1 schematic?
- Re: gEDA-user: Fwd: [Open-graphics] How to get more eyes on OGD1 schematic?
- Re: gEDA-user: Tiling of PCB generated gerber files
- Re: gEDA-user: Fwd: [Open-graphics] How to get more eyes on OGD1 schematic?
- Re: gEDA-user: Fwd: [Open-graphics] How to get more eyes on OGD1 schematic?
- Re: gEDA-user: multi-part symbols [was: OGDI]
- Re: gEDA-user: CVS PCB
- Re: gEDA-user: Olimex and PCB?
- Re: gEDA-user: basic anti-EMI design q
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