[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]

Re: gEDA-user: problem

Dan McMahill wrote: 
Stuart Brorson wrote:

Is there a free software tool to perform a layout extraction to get the
parasitics associated with the layout?




For IC design/layout, I believe that the open-source tool Magic will
extract the parasitics to a SPICE netlist.
For PCB layout, there is no tool, at least as far as I know.  The
reason is that the PCB fab process is less well characterized & more
variable than the IC process.  Also, real models for the parts used
don't exist.  Most op-amps, etc., provide only macromodels, which
don't capture this kind of info.


If in fact magic does (which I'd be suprised if it did or if it does I'd be suprised if it is anything beyond some very basic stuff), then it should be pretty easy to adapt what they do to board layout. Anyone around with inside knowledge of magic who can comment on this?

I'll go ahead and correct myself. Took a look at some magic docs which seem to indicate magic does RC extraction where you can do coupled capacitances. So my question now is more if anyone here knows if it does a decent job. This would seem to be likely starting point if anyone wanted to make a board level extracter. I'll bet 90% of the work is getting the layout data to the correct form for the extracter and figuring out what to do with the resulting data. I figure for all actual devices, you just "black box" them.

-Dan