Re: gEDA-user: problem

[Mike Jarabek <mjarabek@xxxxxxxxx>]

Hi,

Stuart Brorson wrote:
> > Is there a free software tool to perform a layout extraction to get the
> > parasitics associated with the layout?
> >   
>
> For IC design/layout, I believe that the open-source tool Magic will
> extract the parasitics to a SPICE netlist. 
>
> For PCB layout, there is no tool, at least as far as I know.  The
> reason is that the PCB fab process is less well characterized & more
> variable than the IC process.  Also, real models for the parts used
> don't exist.  Most op-amps, etc., provide only macromodels, which
> don't capture this kind of info.
>
> Stuart
We do this thing all the time for $$$.  For the most part the commercial
tools we use do a transmission line simulation on the connectivity extracted
from the layout.  The process goes roughly like this:

    1) Load your board layout into the tool, or use placement information
to get distances.  The electrical characteristics and stackup of the PCB
are needed.
    2) Select the nets you want to simulate
    3) Select models for the drivers and recievers (*)
    4) Extract models for the nets you want to simulate.  These models include
drivers, receivers, vias and of course, transmission lines.
    5) Simulate each net under min-typ-max conditions, maybe do some combinations
of min driver-max receiver etc.
    6) Look at the waveforms for reflections and other undesired effects.
 Add terminations or change routing and go back to step 1 until things are
good.
    7) Write report to send to customer.
    8) Collect cheque.

In our Open source world we have tools to do most of these steps, we are
only really missing the extraction step.  While this functionality does not
exist today.. I can imagine it to be a lot easier to implement now that PCB
has a HID layer....


(*) The models used for `slow' (<1GHz) modeling are usually IBIS models
which are I-V and V-T curves along with RLC models for the pins.  How long
before gnucap or TCL spice can support those models natively?
-- 
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                              Mike Jarabek
                                FPGA/ASIC Designer
 http://www.istop.com/~mjarabek
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