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Re: gEDA-user: problem

To: geda-user@xxxxxxxx
Subject: Re: gEDA-user: problem
From: sdb@xxxxxxxxxx (Stuart Brorson)
Date: Sun, 5 Mar 2006 15:01:04 -0500 (EST)
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In-reply-to: <20060305164508.GC6388@kestrel> from "Karel Kulhavy" at Mar 05, 2006 05:45:08 PM
Reply-to: geda-user@xxxxxxxx
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> Is there a free software tool to perform a layout extraction to get the
> parasitics associated with the layout?

For IC design/layout, I believe that the open-source tool Magic will
extract the parasitics to a SPICE netlist. 

For PCB layout, there is no tool, at least as far as I know.  The
reason is that the PCB fab process is less well characterized & more
variable than the IC process.  Also, real models for the parts used
don't exist.  Most op-amps, etc., provide only macromodels, which
don't capture this kind of info.

Stuart

Follow-Ups:
- Re: gEDA-user: problem
  - From: al davis
- Re: gEDA-user: problem
  - From: Dan McMahill
- Re: gEDA-user: problem
  - From: Mike Jarabek

References:
- Re: gEDA-user: problem
  - From: Karel Kulhavy

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