Re: gEDA-user: problem

[Karel Kulhavy <clock@xxxxxxxxxxxxx>]

On Wed, Mar 01, 2006 at 09:55:11AM -0500, Stuart Brorson wrote:
> I've done boards with 622Mbps parallel busses and 2.5Gbps diff traces
> on FR-4 in the past.  The boards had through vias carefully placed at
> either the source or termination of the signal path.  I don't think
> you'll have a problem, as long as you don't put the vias in the middle
> of your transmission line.  Of course, you want to carefully terminate 
> your transmission lines.
> 
> Think of it this way: 2.5Gbps optical transceivers come with
> through-hole pins, which are much nastier than a small via.  But they
> work fine.  An 0805 resistor pad presents much larger capacitance than
> a small via, and yet folks use them all the time for termination &
> they work (although I agree that 0603 is better, depending upon your
> trace widths).  Finally, lots of 2.5Gbbps <-> 622Mbps SERDES chips
> come in BGA packages, requiring you to route the high speed signal
> through a BGA pin field, which is a nasty electromagnetic
> environment, but they work fine too.
> 
> There is a lot of work out there on via models & the effects of vias
> on high-speed signals.  I suggest you Google around on terms like "via
> signal integrity" and read what experts say about this stuff.  Also,
> Howard Johnson's book is a must-read on the subject: 
> 
> http://www.sigcon.com/bookHSDD.htm

Unfortunately the URL doesn't contain almost any information. This one is better:
http://en.wikipedia.org/wiki/Signal_integrity

Is there a free software tool to perform a layout extraction to get the
parasitics associated with the layout?

CL<