Do you have a way to tell how the interference is getting in? Is it
the supplies or the signal lines?
The only thing I've *seen* is a pulse on the latch line from the
computer to the latch. Remember, I'm just using the parallel port,
and there's a 10 foot ribbon cable connecting it to the board. It's
one of the things I'm trying to get rid of ;-) However, the pulse
looked digital, not like EMI, except that the software couldn't have
put it there (the timing didn't match the "real" signals).
Occasionally I see the results of glitches on the LCD panels, which
means the 9600 baud line is getting corrupted some too. But since
it's bit-banged, that could be the latches too.
In your case, I'd look at using opto isolators or transformers where
possible for driving those off board signals. That confines the
currents induced in that loop to a specific spot which doesn't
include your power supplies.
I was planning on FETs for the same reason; the high impedance on the
gate (inherent and resistors) provides a lot of isolation; I don't
*need* opto isolation just for the electricals; it's all +5 signaling.
One of the first steps when I get serious about it is to design the
I/O blocks, and post them. There's a couple of stages of filtering in
them, yet they should still be usable as generic three-state
bidirectional ports.
If the supply into your board is particularly nasty, which is likely
the case, at a minimum you should put some filtering on it right
where it comes in.
The switcher's app notes talk about those.
Be sure and address both differential and common mode signals. X
and Y caps in line filtering terms. In other words, put some C
between the lines and also to ground.
The switcher only provides +5 and ground. What's the third line?