Re: gEDA-user: New project release

[Dan McMahill <dan@xxxxxxxxxxxx>]

Vanessa Dannenberg wrote:
> On Sunday 12 March 2006 20:02, Dan McMahill wrote:
>
> Do you have docs for the eagle netlist format? Or for
>
> >  that matter, does it look fairly simple? If so, it shouldn't be hard to
>
> >  make one.


> Netlist
>
> Exported from Quickscan-0.1.2.sch at 3/12/2006 20:14:27
>
> EAGLE Version 4.16 Copyright (c) 1988-2005 CadSoft
>
> Net Part Pad Pin Sheet
>
> GND U$1 1 GND(1) 1
>
> U$1 12 GND(12) 1
>
> U$1 A GND(A) 1

> And so on. Pretty simple format, but quite different from what PCB wants.
>
> (U$1 actually is not an IC by the way, it's a connector I forgot to give 
> a name to :-)

So it looks like the rule is if you have 5 fields, the first one is the 
net name, otherwise you continue on the same net?  I think I get what 
"Part" and "Pad" are but I'm not so clear about "Pin" and "Sheet".  It 
also looks like the "Pad" part goes by name instead of by a number.

In PCB, you have something like:

unnamed_net7    C2-1 U1-8
Vcc     R8-2 R10-2 C10-2 U1-13 C12-1 C4-2 R4-2 U1-15 C9-2 TP1-1 X1-2 
C11-1 U1-10
unnamed_net6    R10-1 Q2-3 U1-2

where the first field is netname and after that is is a list of 
Refdes-Pin.  What I'm not sure of is if the pin is the pin number (I 
think it is) or the pin name.  In PCB, there is a difference.

Anyway, without actually running it, something like this should do it:

awk '/^Net / {if(state==0){state=1; next;}} state==1{if(NF == 
5){printf("\n%s %s-%s ", $1, $2, $3);} else if(NF == 4){printf("%s-%s ", 
$1, $2);} } END{printf("\n");}' eagle.net > pcb.net


There will probably some garbage at the end of the file you'll want to 
detect and not spit out.  This should give a netlist which PCB can load. 
The biggest thing I'm concerned with is the pin name vs pin number 
thing.  I got confused reading the code, you might try an experiment on 
a footprint with pin names != pin numbers.

Hope this helps.

-Dan