Karel Kulhavy wrote:
On Thu, Mar 02, 2006 at 03:05:35PM -0800, joeft wrote:Again, you'll need to check the manufacturer's data to find specs appropriate for the caps you are using. For small (0603) SM packages, ESR can be just a few milli-ohms. Also be aware that the ESL and parasitic inductances and capacitances resulting from your layout must be accounted for. You can simulate this, but you will have to make the board parasitics part of your simulation. Getting accurate values for these can be a challenge. For your situation you might consider placing a 100 pF cap as close as possible to the part which you believe is causing the interference. In addition place a .01 uF cap very close to the first cap. Then maybe add a 0.1 uF cap as close as possible to the first two. Connect power to this circuit via a ferrite bead. Use the smallest body size for the caps you can and don't get them in any higher voltage than you need for reliability (high voltage means larger body size which means more inductance in the caps). Keep all traces short and make sure the caps connect solidly to ground.
If I understand your description correctly, you need to raise the impedance of the 2.5cm wire at 200 MHz to keep it from conducting interference to the outside of the box. Is this wire used for power? If so, get a ferrite core (toroid) and put it over the wire; pass the wire through it a few times if you can.
Also, 100 nF caps may be beyond self resonance at 200 MHz depending on their construction. Check the manufacturer's data sheet. It may help to put a smaller cap (100 pF) in parallel with the 10 & 100 nF if 200 MHz is your problem.
But together with the other caps they form a complex RLC network. What's the typical ESR of these caps so I can simulate it and look what happens there?
CL<
Joe T