Re: gEDA-user: Refdes odd issue

[DJ Delorie <dj@xxxxxxxxxxx>]

This is actually in the documentation.  PCB strips trailing lower case
letters from refdeses when building netlists.  I think the idea was to
name individual gates like U1a, U1b, U1c, etc.


7.5 Netlist File Format
=======================

. . . If a NAME ends with a lower-case letter, all lower-case letters
are stripped from the end of the NAME to determine the matching
layout-name name.  For example:

          Data U1-3 U2abc-4 FLOP1a-7 Uabc3-A9

specifies that the net called "Data" should have pin 3 of U1 connected
to pin 4 of U2, to pin 7 of FLOP1 and to pin A9 of Uabc3.  Note that
element name and pin number strings are case-sensitive.  It is up to
you to name the elements so that their layout-name names agrees with
the netlist.