Re: gEDA-user: basic anti-EMI design q

[John Sheahan <jrsheahan@xxxxxxxxxxxxxxxx>]

> > assuming the latch is cmos,
>
> TTL.

the driver needs to suck up to a mA or so from the input to pull it 
down, so external series R should be of order 100 ohms max.
Is it actually a latch or a flipflop? Ff a posedge flipflop,
parking the clock high will give you more noise margin.
A 1n cap soldered on top of the chip, or under the board, cannot hurt.

> > A somewhat easier solution could be to use a USB io in the interface
> > box - but that does not get rid of the beige box.
>
> Hence the 10baseT port in the new design ;-)

when I get around to upgrading my current home network controller, will
either be ethernet or wifi.  thats got even better isolation, and less 
wires. That HC11 has run forth (runtime extensible) for quite a few 
years now.

> > A fet gate is only high impedance at DC. All that gate-drain capacitance
> > matters.
>
> Oh crap, you're right.  Still, I was planning on a 100k or more
> resistor in series with the gates.  Sufficient?  Or plan on an opto?

I have not really seen issues backdriving through a fet. Usually all 
that happens is the miller effect slows switching, but that should not
 be an  issue for you.
If you want to get carried away, add a zener to clamp the gate positive 
voltage excursion.  If what you are driving is both low impedance and 
has sharp spikes, you can couple D-> G, overvoltage the gate oxide and 
let the magic smoke out.   The fet helps to save itself by
turning on as hard as it can during this event, which usually saves things.
You could also add capacitance gate-source if the objective is to 
minimize D -> gate -> driver effects.


Usually if you are trying to minimize external effects you minimize
impedance on your internal nodes. And maximize coupling impedance - 
hence the pi filters you mentioned.

> Actually, the drive FETS have both a resistor and a zener in series,
> so that a floating I/O will drive neither FET.

neither fet?? So its a push-pull output?  I don't follow. I'll wait for 
the circuit.

  It's a funny circuit,
> and I probably should work on that first and post it.  And the I/O
> line has a pair of inductors on it (LCL filter), probably a 12MHz low
> pass filter.