Re: gEDA-user: nets in symbols

[Seb James <seb@xxxxxxxxxxxx>]

On Tue, 2007-03-06 at 18:58 -0500, John Luciani wrote:
> On 3/6/07, Marc Moreau <lares.moreau@xxxxxxxxx> wrote:
> > OKay...  After some poking around, I found this...
> >
> > I have been able to verify, but IIRC, we used to be able to have U1a, U1b etc for different slots within the same device.
> >
> > Trying that anew today. It doesn't work.  Netlist doesn't recognize them as the same, and neither does PCB.  I think something changed.
> >
> > Can someone verify that I am remembering correctly.
> >
> 
> You are remembering correctly. From the PCB documentation ---
> 
> If a NAME ends with a lower-case letter,
> all lower-case letters are stripped from the end of the NAME to determine the
> matching layout-name name.  For example:
> 
>    Data U1-3 U2abc-4 FLOP1a-7 Uabc3-A9
> 
> specifies that the net called "Data" should have
> pin 3 of U1 connected to pin 4 of U2, to pin 7 of
> FLOP1 and to pin A9 of Uabc3.  Note that element name and
> pin number strings are case-sensitive.
> It is up to you to name the elements so that their layout-name names
> agrees with the netlist.
> 
> (* jcl *)

So what to do with my design? I don't think I can work around this, so
where in the code shall I look to fix this?

Seb



_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user