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Re: gEDA-user: What's your way of syncing CPLD design and gschem symbols???

Actually, one thing I have dreamed about is incorporating a method
into gnetlist to read a .ucf (Xilinx) or .pin (Altera) file to get
pin-outs for a large FPGA. Then, you'd just stick a big box (or bunch
of boxes) onto your schematic representing the device. The box would
have a bunch of named pins, but no pin nos. You'd wire nets to the
pins as usual. Then you'd stick somethign like a .include directive onto the same page. The .include directive would
point to the .pin file, and be bound somehow to the big FPGA box
(maybe by sharing refdes). Then, gnetlist would find the .include, open
the corresponding .pin file, and use it to stick the device's pins
into teh output netlist.

This scheme makes design easy, but is bad for service, since the pins
are not annotated onto teh schematic.  It would require the service
guy to have a set of schematics and printouts of the .pin files to
work from.  Maybe not such a big deal.....

FWIW, Steve -- one of the Free Doggers here in Boston -- will talk
about his FPGA flow at our gathering tonight.  I anticipate he will
have some interesting ideas about how to handle the pin issue.

Stuart


On Thu, 8 Mar 2007, Andy Peters wrote:

On Mar 8, 2007, at 9:35 AM, Christoph LECHNER wrote:

Hi!

How do you keep your Xilinx CPLD design in sync w/
your gschem symbol files?

I mean, after you have drawn all your schematics and
build up the essentials of your CPLD design (esp. the
pins must exist :)), when doing the PCB artwork shuffling
the CPLD pins can give a really improved PCB layout ...

But the problem for me was to keep the symbol in sync
w/ the Xilinx Fitter report, so to do the work auto-
matically I hacked a Perl script (~6kB) last year,
but before adding some required upgrades & improvements
to the script I just wanted to ask how you do the sync
job!

For those not familiar with the Xilinx report files
I added a example Xilinx pin-out report for a small
Xilinx device (sorry for the attachment!)
Files with this structure are converted to symbols.

It might be easier to work backwards, from the schematic, and have it back-annotate into the .ucf (user constraint file), which is the file used by the Xilinx tools for pinouts (and timing specs, etc etc). It gets even more complicated when schematic net names don't match the CPLD design pin names, or when you connect the same schematic net to two FPGA pins (like when doing external clock feedback).

This isn't really a problem for small CPLDs but it's a right royal PITA with large FPGAs.

-a


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