Re: gEDA-user: What's your way of syncing CPLD design and gschem symbols???

[Andy Peters <devel@xxxxxxxxx>]

On Mar 8, 2007, at 11:40 AM, Stuart Brorson wrote:

> Actually, one thing I have dreamed about is incorporating a method
> into gnetlist to read a .ucf (Xilinx) or .pin (Altera) file to get
> pin-outs for a large FPGA.  Then, you'd just stick a big box (or bunch
> of boxes) onto your schematic representing the device.  The box would
> have a bunch of named pins, but no pin nos.  You'd wire nets to the
> pins as usual.  Then you'd stick somethign like a .include  
> directive onto the same page.  The .include directive would
> point to the .pin file, and be bound somehow to the big FPGA box
> (maybe by sharing refdes).  Then, gnetlist would find the .include,  
> open
> the corresponding .pin file, and use it to stick the device's pins
> into teh output netlist.

Seems to me that if there's a way to automagically create a symbol  
with named pins from the .ucf or .pin file, then it shouldn't be all  
that difficult (says the non-programmer) to include the pin numbers?   
One problem with the .include directive is that you have to always  
point to some valid thing, and if you use revision control for your  
FPGA designs (and you should ...) then there's never a guarantee that  
the .ucf lives where the .include directive thinks it lives.  It  
might be easier to simply have a script that asks for the  
correct .ucf and embed the pinouts into the schematic.

Regarding splitting large FPGAs into two or more symbols: there are  
two schools of thought here.  One is that the symbol should reflect  
the design functionality, which makes the symbol design-specific and  
you need to create a new one for each FPGA design.  The second is  
that the symbol should show the FPGA's banks.  I've done the former,  
and if you modify the design and add more pins, then you get into  
modifying the symbol, which can get real ugly real quick.  What we do  
now is create components with a symbol for the power and  
configuration connections, and a symbol for each of the FPGA's I/O  
banks.  For example, the Spartan 3E I'm using in a design has four I/ 
O banks, and each symbol has pin names that match the Xilinx pinouts,  
as well as the VCCIO pins for that bank.  Showing the VCCIO on each  
bank, instead of on the global power symbol, is helpful because Bank  
2 may run at 2.5V and Banks 0, 1 and 3 may be powered by 3.3V, and  
it's really helpful to see that right where you use the pins.

-a




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