[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]

gEDA-user: PCB git bug



   Been playing around with the current git release 1.99z (probably
   unstable?) and I've noticed there is one bug - it always wants to
   complain about a DRC error, no matter if the board is clean. In my
   case, the error seems to be chosen randomly from a perfectly good
   trace, and is almost always a "copper areas too close" error. I'm using
   6/6 mil rules and this is a 44pin 10mm TQFP, as can be seen, the trace
   has more than adequate clearance. (The other DRC error is due to some
   dead copper I think, but nothing to be really concerned about.)

Attachment: Screenshot.png
Description: PNG image


_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user